公开(公告)号：AU583714B2

公开(公告)日：1989-05-04

申请号：AU7012787

申请日：1987-03-18

Applicant: TANDEM COMPUTERS INC

Inventor： LILJA DAVID J ,  ZACHER RICHARD ,  WIERENGA STEVEN W

IPC: G06F11/20 ,  G06F13/22 ,  G06F13/42

Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

公开(公告)号：AU605961B2

公开(公告)日：1991-01-24

申请号：AU2991889

申请日：1989-02-14

Applicant: TANDEM COMPUTERS INC

Inventor： LILJA DAVID J ,  WIERENGA STEVEN W ,  ZACHER RICHARD

IPC: G06F11/20 ,  G06F13/22 ,  G06F13/42 ,  G06F1/04 ,  G06F15/16

Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.