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公开(公告)号：KR880000577B1
公开(公告)日：1988-04-15
申请号：KR830000173
申请日：1983-01-18
Applicant: TANDEM COMPUTERS INC
Inventor： HUMPREY RICHARD A , FISHER STEVEN D , WIERENGA STEVEN W , SJOSTEDT JON
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公开(公告)号：CA1147474A
公开(公告)日：1983-05-31
申请号：CA391315
申请日：1981-12-01
Applicant: TANDEM COMPUTERS INC
Inventor： KATZMAN JAMES A , BARTLETT JOEL F , BIXLER RICHARD M , DAVIDOW WILLIAM H , DESPOTAKIS JOHN A , GRAZIANO PETER J , GREEN MICHAEL D , GREIG DAVID A , HAYASHI STEVEN J , MACKIE DAVID R , MCEVOY DENNIS L , TREYBIG JAMES G , WIERENGA STEVEN W
Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system.
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公开(公告)号：CA1137582A
公开(公告)日：1982-12-14
申请号：CA391316
申请日：1981-12-01
Applicant: TANDEM COMPUTERS INC
Inventor： KATZMAN JAMES A , BARTLETT JOEL F , BIXLER RICHARD M , DAVIDOW WILLIAM H , DESPOTAKIS JOHN A , GRAZIANO PETER J , GREEN MICHAEL D , GREIG DAVID A , HAYASHI STEVEN J , MACKIE DAVID R , MCEVOY DENNIS L , TREYBIG JAMES G , WIERENGA STEVEN W
Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.
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公开(公告)号：AU583714B2
公开(公告)日：1989-05-04
申请号：AU7012787
申请日：1987-03-18
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J , ZACHER RICHARD , WIERENGA STEVEN W
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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公开(公告)号：CA1203027A
公开(公告)日：1986-04-08
申请号：CA419694
申请日：1983-01-18
Applicant: TANDEM COMPUTERS INC
Inventor： HUMPHREY RICHARD A , FISHER STEVEN D , WIERENGA STEVEN W , SJOSTEDT JON
Abstract: A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.
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Patent Agency Ranking
公开(公告)号：CA1142619A
公开(公告)日：1983-03-08
申请号：CA391318
申请日：1981-12-01
Applicant: TANDEM COMPUTERS INC
Inventor： KATZMAN JAMES A , BARTLETT JOEL F , BIXLER RICHARD M , DAVIDOW WILLIAM H , DESPOTAKIS JOHN A , GRAZIANO PETER J , GREEN MICHAEL D , GREIG DAVID A , HAYASHI STEVEN J , MACKIE DAVID R , MCEVOY DENNIS L , TREYBIG JAMES G , WIERENGA STEVEN W
IPC: G06F11/30
Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.
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公开(公告)号：DE3750680T2
公开(公告)日：1995-03-09
申请号：DE3750680
申请日：1987-03-13
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J , ZACHER RICHARD A , WIERENGA STEVEN W
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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公开(公告)号：CA1176338A
公开(公告)日：1984-10-16
申请号：CA391313
申请日：1981-12-01
Applicant: TANDEM COMPUTERS INC
Inventor： KATZMAN JAMES A , BARTLETT JOEL F , BIXLER RICHARD M , DAVIDOW WILLIAM H , DESPOTAKIS JOHN A , GRAZIANO PETER J , GREEN MICHAEL D , GREIG DAVID A , HAYASHI STEVEN J , MACKIE DAVID R , MCEVOY DENNIS L , TREYBIG JAMES G , WIERENGA STEVEN W
IPC: G06F3/00
Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.
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公开(公告)号：DE3752205D1
公开(公告)日：1998-09-03
申请号：DE3752205
申请日：1987-03-13
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J DEPT OF ELECTRIC , ZACHER RICHARD A , WIERENGA STEVEN W
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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公开(公告)号：AU605961B2
公开(公告)日：1991-01-24
申请号：AU2991889
申请日：1989-02-14
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J , WIERENGA STEVEN W , ZACHER RICHARD
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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