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    Microelectronic packages and packaging methods in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles
    1.
    发明专利
    Microelectronic packages and packaging methods in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles 未知

    公开(公告)号：AU3658902A

    公开(公告)日：2002-05-27

    申请号：AU3658902

    申请日：2001-11-07

    Applicant: UNITIVE ELECTRONICS INC

    Inventor： RINNE GLENN A

    IPC: H01L25/065

    Abstract: Microelectronic packages include a first microelectronic substrate, a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate, and first solder bumps between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate, that connect the second microelectronic substrate to the first microelectronic substrate and that are confined to within the edge of the second microelectronic substrate. The edge of the second microelectronic substrate is adjacent the vertex of the acute angle. A third microelectronic substrate also may be provided on the first microelectronic substrate that laterally overlaps the second microelectronic substrate. Second solder bumps connect the third microelectronic substrate to the first microelectronic substrate. The second and third microelectronic substrates may be oriented parallel to one another at the acute angle relative to the first microelectronic substrate. Alternatively, second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, wherein the second edge of the third microelectronic substrate is adjacent the vertex and wherein the first edge of the third microelectronic substrate is opposite the vertex.

    Trilayer/bilayer solder bumps and fabrication methods therefor
    2.
    发明专利
    Trilayer/bilayer solder bumps and fabrication methods therefor 未知

    公开(公告)号：AU6123401A

    公开(公告)日：2001-12-03

    申请号：AU6123401

    申请日：2001-05-07

    Applicant: UNITIVE ELECTRONICS INC

    Inventor： RINNE GLENN A

    IPC: H01L21/48 ,  H01L21/60 ,  H05K3/34

    Abstract: Solder bumps are fabricated by plating a first solder layer on an underbump metallurgy, plating a second solder layer having higher melting point than the first solder layer on the first solder layer and plating a third solder layer having lower melting point than the second solder layer on the second solder layer. The structure then is heated to below the melting point of the second solder layer but above the melting point of the first solder layer and the third solder layer, to alloy at least some of the first solder layer with at least some of the underbump metallurgy and to round the third solder layer. Accordingly, a trilayer solder bump may be fabricated wherein the first and third layers melt at lower temperatures than the second solder layer, to thereby round the outer surface of the solder bump and alloy the base of the solder bump to the underbump metallurgy, while allowing the structure of the intermediate layer to be preserved. Solder bump fabrication as described above may be particularly useful with lead-tin solder wherein the first solder layer is eutectic lead-tin solder, the second solder layer is lead-tin solder having higher lead content than eutectic lead-tin solder and the third solder layer is eutectic lead-tin solder. In yet other embodiments, the thickness and/or composition of the outer underbump metallurgy layer and/or of the first solder layer may be selected so that upon heating, sufficient tin from the first solder layer is alloyed with at least some of the outer underbump metallurgy layer, such that the first solder layer is converted to a fourth solder layer having the same lead content as the second solder layer. Bilayer solder bumps thereby may be provided.

    MICROELECTRONIC PACKAGES IN WHICH SECOND MICROELECTRONIC SUBSTRATES ARE ORIENTED RELATIVE TO FIRST MICROELECTRONIC SUBSTRATES AT ACUTE ANGLES
    3.
    发明专利
    MICROELECTRONIC PACKAGES IN WHICH SECOND MICROELECTRONIC SUBSTRATES ARE ORIENTED RELATIVE TO FIRST MICROELECTRONIC SUBSTRATES AT ACUTE ANGLES 未知

    公开(公告)号：MY126102A

    公开(公告)日：2006-09-29

    申请号：MYPI20015186

    申请日：2001-11-10

    Applicant: UNITIVE ELECTRONICS INC

    Inventor： RINNE GLENN A

    IPC: H05K1/11 ,  H01L25/065 ,  H05K1/14

    Abstract: MICROELETRONIC PACKAGES INCLUDE A FIRST MICROELECTRONIC SUBSTRATE, A SECOND MICROELECTRONIC SUBSTRATE THAT IS ORIENTED AT AN ACUTE ANGLE RELATIVE TO THE FIRST AND SECOND MICROELECTRONIC SUBSTRATE AND FIRST SOLDER BUMPS BETWEEN THE FIRST AND SECOND MICROELECTRONIC SUBSTRATES, ADJACENT AN EDGE OF THE SECOND MICROELECTRONIC SUBSTRATE, THAT CONNECT THE SECOND MICROELECTRONIC SUBSTRATE TO THE FIRST MICROELECTRONIC SUBSTRATE AND THAT ARE CONFINED TO WITHIN THE EDGE OF THE SECOND MICROELECTRONIC SUBSTRATE.. THE EDGE OF THE SECOND MICROELECTRONIC SUBSTRATE IS ADJACENT THE VERTEX OF THE ACUTE ANGLE.@A THIRD MICROELECTRONIC SUBSTRATE ALSO MAY BE PROVIDED ON THE FIRST MICROELECTRONIC SUBSTRATE THAT LATERALLY OVERLAPS THE SECOND MICROELECTRONIC SUBSTRATE. SECOND SOLDER BUMPS CONNECT THE THIRD MICROELECTRONIC SUBSTRATE TO THE FIRST MICROELECTRONIC SUBSTRATE. THE SECOND AND THIRD MICROELECTRONIC SUBSTRATES MAY BE ORIENTED PARALLEL TO ONE ANOTHER AT THE ACUTE ANGLE RELATIVE TO THE FIRST MICROELECTRONIC SUBSTRATE. ALTERNATIVELY, SECOND SOLDER BUMPS ARE ADJACENT A SECOND EDGE OF THE THIRD MICROELECTRONIC SUBSTRATE AND OPPOSITE A SECOND EDGE OF THE THIRD MICROELECTRONIC SUBSTRATE IS ADJACENT THE VERTEX AND WHEREIN THE FIRST EDGE OF THE THIRD MICROELECTRONIC SUBSTRATE IS OPPOSITE THE VERTEX.

    Methods and systems for attaching substrates to one another using solder structures having portions with different melting points
    4.
    发明专利
    Methods and systems for attaching substrates to one another using solder structures having portions with different melting points 未知

    公开(公告)号：AU3046802A

    公开(公告)日：2002-05-21

    申请号：AU3046802

    申请日：2001-11-05

    Applicant: UNITIVE ELECTRONICS INC

    Inventor： RINNE GLENN A

    IPC: B23K1/00 ,  B23K35/00 ,  B23K35/26 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34

    Abstract: A first substrate is attached to a second substrate by providing solder structures that include a first portion adjacent the second substrate that has a first melting point, and a second portion adjacent the first substrate that has a second melting point that is lower than the first melting point. The solder structures then are heated to a first temperature that is at or above the second melting point but below the first melting point, to melt the second portions. Simultaneous with the heating of the solder structures to the first temperature, the first substrate is attached to the second substrate while the second portions are melted. Finally, the solder structures are heated to a second temperature that is above the first temperature, to alloy at least some of the first portions and the second portions. Accordingly, low temperature joining and/or positioning of the first substrate relative to the second substrate may be performed, followed by conversion of at least part of the solder structures to a higher melting point alloy, thereby allowing a reduced creep rate.

    MICROELECTRONIC PACKAGES AND PACKAGING METHODS IN WHICH SECOND MICROELECTRONIC SUBSTRATES ARE ORIENTED RELATIVE TO FIRST MICROELECTRONIC SUBSTRATES AT ACUTE ANGLES
    7.
    发明申请
    MICROELECTRONIC PACKAGES AND PACKAGING METHODS IN WHICH SECOND MICROELECTRONIC SUBSTRATES ARE ORIENTED RELATIVE TO FIRST MICROELECTRONIC SUBSTRATES AT ACUTE ANGLES 审中-公开
    第二微电子基板的微电子封装和封装方法相对于急性角度的第一微电子基板

    公开(公告)号：WO0241398A9

    公开(公告)日：2003-10-02

    申请号：PCT/US0147372

    申请日：2001-11-07

    Applicant: UNITIVE ELECTRONICS INC ,  RINNE GLENN A

    Inventor： RINNE GLENN A

    IPC: H01L25/065

    CPC classification number: H05K1/11 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2224/0401

    Abstract: Microelectronic packages include a first microelectronic substrate, a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate, and first solder bumps between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate, that connect the second microelectronic substrate to the first microelectronic substrate and that are confined to within the edge of the second microelectronic substrate. The edge of the second microelectronic substrate is adjacent the vertex of the acute angle. A third microelectronic substrate also may be provided on the first microelectronic substrate that laterally overlaps the second microelectronic substrate. Second solder bumps connect the third microelectronic substrate to the first microelectronic substrate. The second and third microelectronic substrates may be oriented parallel to one another at the acute angle relative to the first microelectronic substrate. Alternatively, second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, wherein the second edge of the third microelectronic substrate is adjacent the vertex and wherein the first edge of the third microelectronic substrate is opposite the vertex.

    Abstract translation: 微电子封装包括第一微电子衬底，相对于第一微电子衬底定向成锐角的第二微电子衬底以及邻近第二微电子衬底边缘的第一和第二微电子衬底之间的第一焊料凸点， 第二微电子衬底到第一微电子衬底并被限制在第二微电子衬底的边缘内。 第二微电子衬底的边缘与锐角的顶点相邻。 也可以在第一微电子衬底上提供第三微电子衬底，其横向地与第二微电子衬底重叠。 第二焊料凸块将第三微电子衬底连接到第一微电子衬底。 第二和第三微电子衬底可以相对于第一微电子衬底以锐角相互平行取向。 或者，第二焊料凸块与第三微电子衬底的第一边缘相邻并且与第三微电子衬底的第二边缘相对，其中第三微电子衬底的第二边缘与顶点相邻，并且其中第三微电子衬底的第一边缘是 顶点对面

    MICROELECTRONIC PACKAGES AND PACKAGING METHODS IN WHICH SECOND MICROELECTRONIC SUBSTRATES ARE ORIENTED RELATIVE TO FIRST MICROELECTRONIC SUBSTRATES AT ACUTE ANGLES
    9.
    发明申请
    MICROELECTRONIC PACKAGES AND PACKAGING METHODS IN WHICH SECOND MICROELECTRONIC SUBSTRATES ARE ORIENTED RELATIVE TO FIRST MICROELECTRONIC SUBSTRATES AT ACUTE ANGLES 审中-公开
    微电子封装和包装方法，其中第二微电子衬底相对于第一微电子衬底在急性角度取向

    公开(公告)号：WO0241398A3

    公开(公告)日：2003-04-10

    申请号：PCT/US0147372

    申请日：2001-11-07

    Applicant: UNITIVE ELECTRONICS INC ,  RINNE GLENN A

    Inventor： RINNE GLENN A

    IPC: H01L25/065

    CPC classification number: H05K1/11 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2224/0401

    Abstract: Microelectronic packages include a first microelectronic substrate, a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate, and first solder bumps between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate, that connect the second microelectronic substrate to the first microelectronic substrate and that are confined to within the edge of the second microelectronic substrate. The edge of the second microelectronic substrate is adjacent the vertex of the acute angle. A third microelectronic substrate also may be provided on the first microelectronic substrate that laterally overlaps the second microelectronic substrate. Second solder bumps connect the third microelectronic substrate to the first microelectronic substrate. The second and third microelectronic substrates may be oriented parallel to one another at the acute angle relative to the first microelectronic substrate. Alternatively, second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, wherein the second edge of the third microelectronic substrate is adjacent the vertex and wherein the first edge of the third microelectronic substrate is opposite the vertex.

    Abstract translation: 微电子封装包括第一微电子衬底，相对于第一微电子衬底以锐角定向的第二微电子衬底，以及在第一微电子衬底和第二微电子衬底之间邻近第二微电子衬底的边缘的第一焊料凸点， 第二微电子衬底连接到第一微电子衬底并且被限制在第二微电子衬底的边缘内。 第二微电子衬底的边缘与锐角的顶点相邻。 还可以在第一微电子衬底上提供第三微电子衬底，其横向地重叠第二微电子衬底。 第二焊料凸块将第三微电子衬底连接到第一微电子衬底。 第二和第三微电子衬底可以相对于第一微电子衬底以锐角彼此平行取向。 或者，第二焊料凸块邻近第三微电子衬底的第一边缘并与第三微电子衬底的第二边缘相对，其中第三微电子衬底的第二边缘邻近顶点，并且其中第三微电子衬底的第一边缘是 在顶点的对面。

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