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    BiCMOS logic gate having linearly operated load FETs
    91.
    发明授权
    BiCMOS logic gate having linearly operated load FETs 失效
    BiCMOS逻辑门具有线性操作的负载FET

    公开(公告)号：US5124580A

    公开(公告)日：1992-06-23

    申请号：US693815

    申请日：1991-04-30

    Applicant: James A. Matthews ,  Geert Rosseel

    Inventor： James A. Matthews ,  Geert Rosseel

    IPC: H03K17/567 ,  H03K19/08 ,  H03K19/086 ,  H03K19/0944

    CPC classification number: H03K19/09448

    Abstract: A BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a p-channel metal-oxide-semiconductor (PMOS) transistor. An emitter follower, having its base coupled to the collector of one of the bipolar transistors and its collector connected to the first power supply potential, provides the output signal. NMOS transistors are used as current sources for biasing the emitter-coupled pair and the emitter follower. A circuit means provides a feedback signal coupled to the gates of the PMOS transistors for dynamically controlling the load resistance presented to said emitter coupled pair.

    Abstract translation: BiCMOS逻辑电路利用发射极耦合的双极晶体管对将输入信号与逻辑参考电平进行差分比较。 每个双极晶体管由p沟道金属氧化物半导体（PMOS）晶体管电阻负载。 射极跟随器，其基极耦合到双极晶体管之一的集电极，并且其集电极连接到第一电源电位，提供输出信号。 NMOS晶体管用作用于偏置发射极耦合对和射极跟随器的电流源。 电路装置提供耦合到PMOS晶体管的栅极的反馈信号，用于动态地控制呈现给所述发射极耦合对的负载电阻。

    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS
    93.
    发明公开
    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
    系统维护工作人员培训

    公开(公告)号：EP3161616A2

    公开(公告)日：2017-05-03

    申请号：EP15815691.9

    申请日：2015-06-26

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

    IPC: G06F9/30

    CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

    Abstract translation: 公开了可扩展的宽操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。

    System with wide operand architecture, and method
    96.
    发明公开
    System with wide operand architecture, and method 有权
    系统管理员Operandenarchitektur und Verfahren

    公开(公告)号：EP2241968A2

    公开(公告)日：2010-10-20

    申请号：EP10160103.7

    申请日：1999-08-24

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： Hansen, Craig

    IPC: G06F9/30

    CPC classification number: G06F9/30014 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3885 ,  G06F12/0886

    Abstract: A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).

    Abstract translation: 具有访问单元的四个副本的通用处理器，具有访问指令获取队列A队列（101-104）。 每个A队列（101-104）耦合到耦合到两个访问功能单元A（109-116）的访问寄存器文件AR（105-108）。 在典型的实施例中，处理器的每个线程可以具有六十四个通用寄存器的数量级。 访问单元通过四个同时执行的线程独立地起作用，并且通过执行加载和存储指令来执行算术和分支指令以及访问存储器来进行每个计算控制流程。 这些访问单元还提供广泛的操作数说明。 这八个访问功能单元A（109-116）产生访问寄存器文件（105-108）和存储器地址到共享存储器系统（117-120）的结果。

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