公开(公告)号：WO2005008410A3

公开(公告)日：2005-01-27

申请号：PCT/US2004/022126

申请日：2004-07-12

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F12/00

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

公开(公告)号：WO2016003820A9

公开(公告)日：2016-01-07

申请号：PCT/US2015/038078

申请日：2015-06-26

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F9/30

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

公开(公告)号：EP3276486A1

公开(公告)日：2018-01-31

申请号：EP17183101.9

申请日：2017-07-25

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F7/544

CPC classification number: G06F7/523 ,  G06F7/5045 ,  G06F7/5443 ,  G06F2207/3828

Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations are disclosed.

Abstract translation: 公开了一种用于对需要大量乘法和累加的向量操作数执行外积和外积累积操作的处理器和方法。

公开(公告)号：EP3161616A2

公开(公告)日：2017-05-03

申请号：EP15815691.9

申请日：2015-06-26

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

Abstract translation: 公开了可扩展的宽操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。

公开(公告)号：EP1652090A2

公开(公告)日：2006-05-03

申请号：EP04756853.0

申请日：2004-07-12

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F12/00

CPC classification number: G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.