中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.036 seconds)

    PROGRAMMABLE PROCESSOR AND METHOD WITH WIDE OPERATIONS
    1.
    发明申请
    PROGRAMMABLE PROCESSOR AND METHOD WITH WIDE OPERATIONS 审中-公开

    公开(公告)号：WO2005008410A3

    公开(公告)日：2005-01-27

    申请号：PCT/US2004/022126

    申请日：2004-07-12

    Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

    Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

    IPC: G06F12/00

    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

    SYSTEM AND METHOD FOR PERFORMING MULTIPLICATION
    2.
    发明申请
    SYSTEM AND METHOD FOR PERFORMING MULTIPLICATION 审中-公开

    公开(公告)号：WO2003021423A3

    公开(公告)日：2003-03-13

    申请号：PCT/US2002/027970

    申请日：2002-09-04

    Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

    Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

    IPC: G06F7/48

    Abstract: A vector-matrix multiplier unit fully utilizes a 128x128b data path for operand sizes from 8 to 128b and operand types including signed, unsigned or complex, and fixed-, floating-point, polynomial, or Galois-field while maintaining full internal precision. The present disclosure provides a system and method for improving the performance of general-purpose processor, by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multipliers regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

    SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR
    3.
    发明申请
    SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR 审中-公开
    用于实现宽带处理器的矩阵多项式单元的系统和方法

    公开(公告)号：WO2003021423A2

    公开(公告)日：2003-03-13

    申请号：PCT/US2002/027970

    申请日：2002-09-04

    Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

    Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

    IPC: G06F7/00

    CPC classification number: G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/57 ,  G06F7/724 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16 ,  G06F2207/3812 ,  G06F2207/382 ,  G06F2207/3824 ,  G06F2207/3828

    Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multipliers regardsless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

    Abstract translation: 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 随着操作数大小减小，矩阵和向量操作数的元素数量增加，功能单元完全利用128b乘128b乘法器的全部资源，而不考虑操作数大小。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS
    4.
    发明申请
    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开

    公开(公告)号：WO2016003820A9

    公开(公告)日：2016-01-07

    申请号：PCT/US2015/038078

    申请日：2015-06-26

    Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

    Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

    IPC: G06F9/30

    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

    SYSTEM AND METHOD TO IMPLEMENT A CROSS-BAR SWITCH OF A BROADBAND PROCESSOR
    5.
    发明公开
    SYSTEM AND METHOD TO IMPLEMENT A CROSS-BAR SWITCH OF A BROADBAND PROCESSOR 审中-公开
    系统和方法是实现宽带处理器的CROSS-BASS AGE

    公开(公告)号：EP1236090A1

    公开(公告)日：2002-09-04

    申请号：EP00910150.2

    申请日：2000-02-11

    Applicant: Microunity Systems Engineering, Inc.

    Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

    IPC: G06F9/30

    CPC classification number: G06F7/76 ,  G06F9/30018

    Abstract: The present invention provides a cross-bar circuit (100) that implements a switch (115) of a broadband processor. The cross-bar circuit (100) includes: a switch circuit (115) which includes 2m.2n:1 multiplexor circuits (202-204) where each of the 2n:1 multiplexor circuits (202-204) has a unique n-bit index input, one disable input, and a 2n-bit wide source input receives an n-bit index at the n-bit index input, a disable bit at the disable input, and the 2n-bit input source word at the 2n-bit wide source input, and decodes the n-bit index either to select and output as an output destination bit one bit from the 2n-bit input source word if the disable bit has a logic low value; a cache memory (110) that has 2m cache datapath inputs; and 2m cache index input; and a control circuit (105) that has a plurality of control inputs receives the partially decoded instruction information on the plurality of control inputs, provides a second set of the n-bit indexes for the switch circuit (115), and provides the disable bits for the switch circuit (115) where the control circuit (105) is logically coupled to the switch circuit (115) and to the cache memory (110).

    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS
    7.
    发明公开
    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
    系统维护工作人员培训

    公开(公告)号：EP3161616A2

    公开(公告)日：2017-05-03

    申请号：EP15815691.9

    申请日：2015-06-26

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

    IPC: G06F9/30

    CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

    Abstract translation: 公开了可扩展的宽操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。

Patent Agency Ranking