公开(公告)号：EP1018131A1

公开(公告)日：2000-07-12

申请号：EP97926809.1

申请日：1997-06-05

Applicant: Candescent Technologies Corporation

Inventor： HAVEN, Duane, A. ,  LUDWIG, Paul, N. ,  SPINDT, Christopher, J. ,  DOBKIN, Daniel, M.

IPC: H01J1/30

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: A gated electron-emitter is fabricated by a process in which particles (26) are deposited over an insulating layer (24). Gate material is provided over the insulating layer in the space between the particles after which the particles and any overlying material are removed. The remaining gate material forms a gate layer (28A or 48A) through which gate openings (30 or 50) extend at the locations of the removed particles. When the gate material deposition is performed so that part of the gate material extends into the spaces below the particles, the gate openings are beveled. The insulating layer is etched through the gate openings to form dielectric openings (32 or 52). Electron-emissive elements (36A or 56A) are formed in the dielectric openings. This typically involves introducing emitter material through the gate openings into the dielectric openings and using a lift-off layer (34), or an electrochemical technique, to remove excess emitter material.

公开(公告)号：EP1016115A1

公开(公告)日：2000-07-05

申请号：EP98913153.7

申请日：1998-03-24

Applicant: Candescent Technologies Corporation

Inventor： DRUMM, Paul, M.

IPC: H01J29/10

CPC classification number: H01J9/242 ,  H01J29/085 ,  H01J2201/025 ,  H01J2329/00

Abstract: A multi-level conductive matrix structure for separating rows (106, 108) and columns (110-122) of sub-pixels on a faceplate (104) of a flat panel display device is disclosed. The matrix structure has a first plurality of parallel spaced apart conductive ridges having a height, a second plurality of parallel spaced apart conductive ridges having a height higher than the height of the first plurality of conductive ridges, and the height of second conductive ridges decreases to the height of first conductive ridges at intersections of the first and second conductive ridges.

公开(公告)号：EP0998597A1

公开(公告)日：2000-05-10

申请号：EP98906269.0

申请日：1998-02-10

Applicant: Candescent Technologies Corporation

Inventor： PORTER, John, D. ,  CHAKAROVA, Gabriela, S. ,  KNALL, N., Johan ,  SPINDT, Christopher, J.

IPC: C25D5/02 ,  C25D5/48 ,  B23H3/00 ,  H01J1/02 ,  H01J1/62 ,  B44C1/22 ,  H01J9/02

CPC classification number: H01J9/025

Abstract: A method for forming a field emitter structure in which a cavity (208) is formed into an insulating layer (206) overlaying a first electrically conductive layer (202). A second electrically conductive layer (210) with an opening (212) is formed above the cavity. Electron emissive material (214) is deposited directly onto the second electrically conductive layer without first depositing an underlying lift-off layer. Electron emissive material covers the opening in the second electrically conductive layer and forms an electron emissive element (216) within the cavity. A first potential is imparted to the electron emissive element. A second open circuit potential is imparted to the closure layer of electron emissive material. The field emitter structure is exposed to an electrochemical etchant (220) wherein the electrochemical etchant etches electron emissive material which is biased at open circuit potential. Electron emissive material is removed from above the second electrically conductive layer without etching the electron emissive element.

公开(公告)号：EP0995213A1

公开(公告)日：2000-04-26

申请号：EP98922233.6

申请日：1998-05-12

Applicant: Candescent Technologies Corporation

Inventor： CHAKRAVORTY, Kishore, K. ,  ELIZONDO, Philip, J.

IPC: H01J9/02

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: A method for forming a gate electrode comprises depositing a gate metal (604) over an insulating substrate (602) and etching openings in areas of the gate layer which are exposed through a hard mask. The layer of the gate metal (604) is deposited to a thickness approximately the same as the thickness desired for the gate electrode. Next, polymer particles (700) are deposited over the layer of gate metal. A hard mask layer (800) is then deposited over the polymer particles and the layer of gate metal. Then the polymer particles (700) and portions of the hard mask (800) which overlie the polymer particles are removed such that first regions of the gate metal (604) are exposed while second regions remain covered by the hard mask. After openings have been formed completely through the gate metal in the first regions, the remaining portions of the hard mask are removed.

公开(公告)号：EP0971799A1

公开(公告)日：2000-01-19

申请号：EP98903607.4

申请日：1998-01-21

Applicant: Candescent Technologies Corporation

Inventor： DRUMM, Paul, M.

IPC: B05D3/02

CPC classification number: H01J29/327 ,  H01J29/28

Abstract: On a flat panel display structure, having a raised black matrix (200) defining wells within the matrix, is deposited a non-conformal, planar layer of acrylic-containing aluminizing lacquer (208) over a layer of phosphors (206) residing within the wells of the black matrix. A planar layer of catalyst material (210) is deposited over the layer of lacquer (208). A planar aluminum layer (212) is subsequently deposited over the catalytic layer (210). Finally, a baking process is conducted at a temperature such that the lacquer layer (208) and the catalyst layer (210) are cleanly and completely evaporated. This temperature is relatively low so as not to adversely affect the reflectivity of the aluminum layer (212), damage the black matrix material (200), or induce oxidation of phosphors. A substantially planar and mirror-like aluminum surface is achieved.

公开(公告)号：EP0966499A1

公开(公告)日：1999-12-29

申请号：EP98911394.0

申请日：1998-02-27

Applicant: Candescent Technologies Corporation ,  HEWLETT-PACKARD COMPANY

Inventor： PORTER, John, D. ,  CRANE, Scott, J. ,  OBERG, Stephanie, J. ,  JOHNSON, Anthony, W.

IPC: C08J3 ,  C08J5 ,  C08L69 ,  H01J9

CPC classification number: C08J3/096 ,  C08J3/09 ,  C08J5/18 ,  C08J2369/00 ,  H01J9/025 ,  H01J2329/00

Abstract: A liquid chemical formulation suitable for making a thin solid polycarbonate film contains polycarbonate material and a liquid typically capable of dissolving the polycarbonate to a concentration of at least 1 %. The liquid also typically has a boiling point of at least 80 °C. Examples of the liquid include pyridine, a ring-substituted pyridine derivative, pyrrole, a ring-substituted pyrrole derivative, pyrrolidine, a pyrrolidine derivative, chlorobenzene, and cyclohexanone. A liquid film (36A) of the liquid chemical formulation is formed over a substructure (30) and processed to remove the liquid. In subsequent steps, the resultant solid polycarbonate film can serve as a track layer through which charged particles (70) are passed to form charged-particle tracks (72). Apertures (74) are created through the track layer by a process that entails etching along the tracks. The aperture-containing polycarbonate track layer is typically employed in fabricating a gated electron-emitting device.

公开(公告)号：EP0948802A1

公开(公告)日：1999-10-13

申请号：EP97953116.0

申请日：1997-12-18

Applicant: Candescent Technologies Corporation

Inventor： FAHLEN, Theodore, S. ,  CONTE, Alfred, S. ,  DUBOC, Robert, M., Jr. ,  HOPPLE, George, B. ,  O'REILLY, John, K. ,  CHAKAROV, Vasil, M. ,  MARION, Robert, L. ,  CHO, Steven, T. ,  NEIMEYER, Robert, G. ,  SUN, Jennifer, Y. ,  MORRIS, David, L. ,  SPINDT, Christopher, J. ,  NARAYANAN, Kollengode, S.

IPC: H01J9 ,  H01J29 ,  H01J31

CPC classification number: H01J9/242 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/8625 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/8665 ,  Y10T29/49004 ,  Y10T29/49117

Abstract: Methods and structures are provided which support spacer walls (100) in a position which facilitates installation of the spacer walls (100) between a faceplate and backplate of a flat display. In one embodiment, spacer feet (111, 112) are formed at the opposing ends of the spacer wall. Tacking electrodes can be provided on the faceplate to assert an electrostatic force on the spacer feet (111, 112), thereby holding the spacer feet in place during installation of the spacer wall. The spacer wall can be mechanically and/or thermally expanded prior to attaching both ends of the spacer wall to the faceplate. The spacer wall is then allowed to contract, thereby introducing tension into the spacer wall which tends to straighten any inherent wavines in the spacer wall. Alternatively, spacer clips can be clamped onto opposing ends of a spacer wall to support the spacer wall during installation. The spacer clips can provide electrical connections to face electrodes located on the spacer wall.

公开(公告)号：EP0922293A1

公开(公告)日：1999-06-16

申请号：EP97927842.0

申请日：1997-06-05

Applicant: Candescent Technologies Corporation

Inventor： LUDWIG, Paul, N. ,  HAVEN, Duane, A. ,  MACAULAY, John, M. ,  SPINDT, Christopher, J. ,  CLEEVES, James, M. ,  KNALL, N., Johan

IPC: H01J1 ,  H01J9

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: An electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over one of the following layers: the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. The gate openings are then variously employed in forming dielectric openings (56, 58, 80, 114, 128, 144, or 154) through the insulating layer. Electron-emissive elements that can, for example, be shaped like cones (58A or 70A) or like filaments (106B, 116B, 130A, 146A, or 156B) are formed in the dielectric openings.

公开(公告)号：EP1405091A2

公开(公告)日：2004-04-07

申请号：EP01990733.6

申请日：2001-11-28

Applicant: Candescent Technologies Corporation

Inventor： ENACHESCU, Marius ,  BELIKOV, Sergey ,  MEIER, Stephen, F.

IPC: G01R31/28 ,  G01R31/302

CPC classification number: G09G3/006 ,  G01R31/308

Abstract: A method and system (200) for detecting electrical short circuit defects in a plate structure of a flat panel display (205), for example, a field emission display (FED). In one embodiment, the process first applies a stimulation (204) to the electrical conductors of the plate structure. Next, the process creates an infra-red thermal mapping (210) of a cathode region the FED. For example, an infra-red array may be used to snap a picture of the cathode of the FED.Then , the process analyzes (100) the infra-red thermal mapping to determine a region of the FED which contains the electrical short circuit defect (215). Another embodiment localizes the defect to one sub-pixel by performing an infra-red mapping (212) of the region which the previous IR mapping process determined to contain the electrical short circuit defect (215). Then, the process analyzes (100) this infra-red mapping to determine a sub-pixel of the FED which contains the electrical short circuit defect (215).

公开(公告)号：EP1364361A2

公开(公告)日：2003-11-26

申请号：EP02725025.7

申请日：2002-02-26

Applicant: Candescent Technologies Corporation

Inventor： DUNPHY, James, C. ,  HANSEN, Ronald, L. ,  LINDBERG, Brian, E. ,  TRUPPA, Jerome, M. ,  ELLOWAY, Donald, J. ,  AMANIAMPONG, Duke, K.

IPC: G09G3/10

CPC classification number: H01J9/44 ,  G09G3/22 ,  G09G2310/066 ,  H01J2209/0223

Abstract: A circuit and method for turning-on and turning-off elements of an field emission display device to protect against emitter electrode(60) and gate electrode(50) degradation. The circuit(910) includes control logic(916) having a sequencer which in one embodiment can be realized using a state machine. Upon power-on, the control logic sends an enable signal to a high voltage power supply (912) that supplies voltage to the anode electrode (914). At this time a low voltage power supply (918) and driving circuitry (920)are disabled. Upon receiving a confirmation signal from the high voltage power supply, the control logic enables the low voltage power supply which supplies voltage to the driving circuitry (920). Upon receiving a confirmation signal from the low voltage power supply (918), or optionally after expiration of a predetermined time period, the control logic (916) then enables the driving circuitry (920) which drives the gate electrodes (50) and the emitter electrodes (60) which make up the rows and columns of the FED device. Upon power down, the control logic (916) first disables the low voltage power supply (918), then the high voltage power supply (912).