METHOD AND APPARATUS FOR CONVEYING CLOCK-RELATED INFORMATION FROM A TIMING DEVICE

    公开(公告)号:WO2023059401A2

    公开(公告)日:2023-04-13

    申请号:PCT/US2022/040258

    申请日:2022-08-12

    Abstract: A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.

    SYSTEM AND METHOD FOR BYPASS MEMORY READ REQUEST DETECTION

    公开(公告)号:WO2022256153A1

    公开(公告)日:2022-12-08

    申请号:PCT/US2022/028767

    申请日:2022-05-11

    Abstract: System and method for analyzing CXL flits at read bypass detection logic (115) to identify bypass memory read requests (108) and transmitting the identified bypass memory read requests (108) over a read request bypass path (120) directly to a transaction/ application layer (135) of the CXL memory controller (100), wherein the read request bypass path (120) does not include an arbitration/ multiplexing layer (125) and a link layer (130) of the CXL memory controller (100), thereby reducing the latency inherent in a CXL memory controller (100).

    SYSTEM AND METHOD FOR DOUBLE DATA RATE (DDR) CHIP-KILL RECOVERY

    公开(公告)号:WO2022231681A1

    公开(公告)日:2022-11-03

    申请号:PCT/US2022/017289

    申请日:2022-02-22

    Abstract: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.

    METHOD AND APPARATUS FOR READING A FLASH MEMORY DEVICE

    公开(公告)号:WO2022182374A1

    公开(公告)日:2022-09-01

    申请号:PCT/US2021/030191

    申请日:2021-04-30

    Abstract: A method for reading a flash memory device includes storing configuration files of reliability-state Classification Neural Network (CNN) models and Regression Neural Network (RNN) inference models, and storing reliability-state tags corresponding to reliability states. The current number of P/E cycles is identified and a reliability-state CNN model is selected corresponding to the current number of P/E cycles. A neural network operation of the selected reliability-state CNN model is performed to identify a predicted reliability state. Corresponding reliability-state tags are identified and a corresponding RNN inference model is selected. A neural network operation of the selected RNN inference model is performed, using the reliability-state tags as input, to generate output indicating the shape of a threshold-voltage-shift read-error (TVS-RE) curve. Threshold Voltage Shift Offset (TVSO) values are identified corresponding to a minimum value of the TVS-RE curve and a read is performed using a threshold-voltage-shift read at the identified TVSO values.

    HIGH RESOLUTION ANGULAR INDUCTIVE SENSOR AND ASSOCIATED METHOD OF USE

    公开(公告)号:WO2022132229A1

    公开(公告)日:2022-06-23

    申请号:PCT/US2021/039578

    申请日:2021-06-29

    Inventor: SHAGA, Ganesh

    Abstract: An angular position sensor comprising two annular sensors, one annular sensor for generating a coarse resolution time varying signal in the presence of a rotatable inductive coupling element and the other annular sensor for generating a fine resolution time varying signal in the presence of the rotatable inductive coupling element. The rotatable inductive coupling element comprising a first annular portion comprising at least one annular conductive sector and at least one annular non-conductive sector and a second annular portion comprising at least one annular conductive sectors and at least one annular non-conductive sector, wherein the number of annular conductive sectors of the first annular portion and the second annular portion are different. In particular, the annular conductive sectors of the annular portions may comprise 50% or 75% of the total area of the annular portions.

    REGRESSION NEURAL NETWORK FOR IDENTIFYING THRESHOLD VOLTAGES TO BE USED IN READS OF FLASH MEMORY DEVICES

    公开(公告)号:WO2022025976A1

    公开(公告)日:2022-02-03

    申请号:PCT/US2021/012105

    申请日:2021-01-04

    Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

    SYSTEM AND METHOD FOR SYNCHRONIZING NODES IN A NETWORK DEVICE

    公开(公告)号:WO2022019984A1

    公开(公告)日:2022-01-27

    申请号:PCT/US2021/030165

    申请日:2021-04-30

    Abstract: System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal.

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