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    Delay locked loop circuit and semiconductor integrated circuit device
    91.
    发明公开
    Delay locked loop circuit and semiconductor integrated circuit device 有权
    Verzögerungsschleifenschaltung和integrierter Halbleiterschaltkreis

    公开(公告)号：EP1835623A1

    公开(公告)日：2007-09-19

    申请号：EP07000456.9

    申请日：2007-01-10

    Applicant: Renesas Technology Corp.

    Inventor： Kawamoto, Takashi, c/o Hitachi, Ltd.

    IPC: H03L7/081

    CPC classification number: H03L7/0812 ,  H03L7/0891 ,  H03L7/10

    Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

    Abstract translation: 提供了能够避免在延迟锁定环路中产生恒定相位误差的延迟锁定环路故障的技术。 在延迟锁定环电路中，控制电路设置在延迟锁定环的外部，并且在延迟锁定环的相位比较中，控制电路向延迟锁定环输出控制信号，使得相位中的关系 参考信号和输出信号之间的比较偏移设定的周期。

    MICRO PATTERN FORMING MATERIAL, METHOD OF FORMING MICRO RESIST PATTERN AND ELECTRONIC DEVICE
    92.
    发明公开
    MICRO PATTERN FORMING MATERIAL, METHOD OF FORMING MICRO RESIST PATTERN AND ELECTRONIC DEVICE 审中-公开
    微观结构发生材料，用于生产微抗蚀剂结​​构及电子零件

    公开(公告)号：EP1791028A1

    公开(公告)日：2007-05-30

    申请号：EP05780882.6

    申请日：2005-08-23

    Applicant: Renesas Technology Corp. ,  AZ Electronic Materials (Japan) K.K.

    Inventor： ISHIBASHI, Takeo c/o Renesas Technology Corp. ,  TAKAHASHI, K. AZ Electronic Materials(Japan)K.K. ,  TAKANO, Yusuke AZ Electronic Materials(Japan)K.K.

    IPC: G03F7/40 ,  H01L21/027

    CPC classification number: G03F7/40 ,  H01L21/0274 ,  H01L21/3086 ,  H01L21/3088

    Abstract: A fine pattern forming material comprising a water soluble resin of polyvinyl alcohol derivative, etc., a water soluble crosslinking agent of melamine derivative, urea derivative, etc., an amine compound, a nonionic surfactant and water or a solution of a mixture of water and water soluble organic solvent, the solution exhibiting a pH value of >7. This fine pattern forming material is applied onto resist pattern (3) to thereby form coating layer (4), and the coating layer (4) is heated and developed to thereby form crosslinked coating layer (5). The thickness of the crosslinked coating layer is increased by the use of a secondary amine compound and/or tertiary amine compound over that realized when no amine compound is added, while the thickness of the crosslinked coating layer is decreased by the use of a quaternary amine.

    Abstract translation: 精细图案形成材料，其含有聚乙烯醇衍生物等，三聚氰胺衍生物的水溶性交联剂，尿素衍生物等的水溶性树脂胺化合物，非离子表面活性剂和水或水的混合物中的溶液， 和水溶性有机溶剂，将溶液参展的pH值>第七 此微细图案形成材料走上抗蚀剂图案中的应用（3），从而形成涂层（4），并且涂布层（4）被加热并显影，从而形成交联的涂层（5）。 交联的涂层的厚度是通过使用在没有实现当不加入胺化合物的仲胺化合物和/或叔胺化合物的增加，而交联的涂层的厚度是通过使用季胺的减少 ，

    Semiconductor integrated circuit and contactless electronic device using the same
    94.
    发明公开
    Semiconductor integrated circuit and contactless electronic device using the same 有权
    Halbleiterschaltungsanordnung在einerberührungslosenelektronischen Vorrichtung

    公开(公告)号：EP1780660A2

    公开(公告)日：2007-05-02

    申请号：EP06022553.9

    申请日：2006-10-27

    Applicant: Renesas Technology Corp.

    Inventor： Watanabe, Kazuki, c/o Hitachi Ltd.

    IPC: G06K19/07 ,  H02M3/07

    CPC classification number: G06K19/0723 ,  G06K19/0713

    Abstract: A semiconductor integrated circuit (2), provided with a charge pump circuit (9) of low power consumption, maintains an output voltage (VOUT) thereof at a predetermined voltage level without causing current consumption to undergo intermittent variation, and a contactless electronic device (1) using the semiconductor integrated circuit (2). With respective charge pump circuit unit cells (15,19), charge current/discharge current is controlled according to the output voltage (VOUT) of the charge pump circuit (9). The charge pump circuit (9) can maintain the output voltage (VOUT) thereof at the predetermined voltage level without undergoing an intermittent action. The charge current and discharge current are supplied from power supply terminals (PA,PB) of a power supply circuit (3), current control is executed by a transistor, and a voltage outputted according to the output voltage (VOUT) of the charge pump circuit (9) is supplied to the gate of the transistor.

    Abstract translation: 设置有低功耗的电荷泵电路（9）的半导体集成电路（2）将其输出电压（VOUT）维持在预定的电压水平，而不会导致电流消耗发生间歇变化，以及非接触式电子设备 1）使用半导体集成电路（2）。 利用各个电荷泵电路单元（15,19），根据电荷泵电路（9）的输出电压（VOUT）来控制充电电流/放电电流。 电荷泵电路（9）可以将其输出电压（VOUT）保持在预定电压水平，而不会发生间歇动作。 充电电流和放电电流由电源电路（3）的电源端子（PA，PB）提供，电流控制由晶体管执行，并且根据电荷泵的输出电压（VOUT）输出的电压 电路（9）被提供给晶体管的栅极。

    Method for evaluating semiconductor device error and system for supporting the same
    98.
    发明公开
    Method for evaluating semiconductor device error and system for supporting the same 审中-公开
    一种用于在半导体装置的评价缺陷和对应的装置的方法

    公开(公告)号：EP1583007A3

    公开(公告)日：2005-10-26

    申请号：EP05000924.0

    申请日：2005-01-18

    Applicant: Renesas Technology Corp.

    Inventor： Ibe, Hidefumi Hitachi, Ltd. ,  Yahagi, Yasuo Hitachi, Ltd. ,  Kameyama, Hideaki Hitachi, Ltd.

    IPC: G06F17/50 ,  G11C11/412 ,  G06F17/18 ,  G01R31/30

    CPC classification number: G01R31/31816 ,  G01R31/002 ,  G01R31/2849 ,  G01R31/2881 ,  G01R31/30

    Abstract: When resistivity against errors caused by cosmic ray neutrons in a semiconductor device is evaluated, the storage (120) in the evaluation apparatus stores multiple spectrum data of white neutrons having different spectrum shapes, and multiple SEE counts obtained by the white neutron method using this multiple spectrum data. A computing section (100) performs processing, with respect to each spectrum data, to read out the spectrum data from the storage, divide the data into multiple energy groups, calculates and stores a total flux of each energy group. Furthermore, the computing section reads out from the storage, the SEE counts with respect to each of the multiple spectrum data and the total flux of each energy group, substitutes the SEE counts and the total flux into a simultaneous equation, where a product of matrix elements indicating the total flux of each of the energy groups as to each of the multiple spectrum data and vectors indicating the SEE cross section of each of the energy groups represents the SEE count as to each of the multiple spectrum data, and calculates the SEE cross section for each of the energy groups. Subsequently, the computing section performs a calculation so that parameters are calculated, which determine a formula of the approximate function of the SEE cross section as a function of energy, so that computed values of error counts obtained by integration of multiple spectra and the approximate function sufficiently match the actual measured values thereof. With the processing as described above, there has been achieved an error evaluation in the semiconductor device using white neutrons independent from an accelerator.

    Abstract translation: 当针对通过在半导体器件中的宇宙射线的中子引起的错误的电阻率进行评价，在评价装置中的存储装置（120）存储具有不同的频谱形状通过使用该多个白色中子方法得到的白色中子的多个频谱数据和多个SEE计数 光谱数据。 一种计算部（100）执行处理，对于每个光谱数据，从存储读出的谱数据，将数据划分为多个能量组，计算和存储各能量组的总通量。 进一步，运算部从存储中读出时，SEE相对于每个所述多个谱数据和每个能量组的总通量的计数，代入SEE计数和总光通量成的联立方程，矩阵的其中一个产品 关于每个所述多个谱数据和向量元素指示每个能量组的总通量指示每个能量组的SEE截面darstellt的SEE数作为给每个所述多个谱数据，并且计算SEE横 部针对每个能量组。 接着，运算部进行运算所以没有参数被计算，其中确定性矿作为能量的函数的SEE截面的近似函数的公式，所以并计算由多个光谱的积分和近似函数而获得的错误计数的值 充分匹配其实际测量值。 通过如上所述的处理，存在一种使用白色中子从独立于加速器已经达到在误差评价的半导体装置。

    On-screen display unit
    100.
    发明公开
    On-screen display unit 审中-公开
    Bildschirmanzeigevorrichtung

    公开(公告)号：EP1452958A2

    公开(公告)日：2004-09-01

    申请号：EP03022640.1

    申请日：2003-10-06

    Applicant: Renesas Technology Corp. ,  Renesas LSI Design Corporation

    Inventor： Matsumoto, Seiji

    IPC: G06F3/14

    CPC classification number: G09G5/003 ,  G09G2340/12

    Abstract: An on-screen display unit includes OSD RAMs (1a and 1b) each for storing data on one of OSD blocks to be subjected to OSD (on-screen display); a memory bus (11) for transferring data to be stored to the OSD RAMs (1a and 1b) from a CPU (4); and an OSD local bus (12) for transferring the data stored in the OSD RAMs (1a and 1b) to make the OSD. The OSD RAMs (1a and 1b) are supplied with the data to be stored through the control of switches (2a and 2b) alternately, and transfer the stored data to the OSD local bus 12 alternately. The on-screen display unit can cope with a high frequency OSD clock signal, and carry out the OSD normally.

    Abstract translation: 屏幕显示单元包括OSD RAM（1a和1b），每个OSD RAM用于存储要进行OSD（屏幕显示）的OSD块中的一个数据; 存储器总线（11），用于从CPU（4）传送要存储到OSD RAM（1a和1b）的数据; 以及用于传送存储在OSD RAM（1a和1b）中的数据以进行OSD的OSD本地总线（12）。 交替地通过开关（2a和2b）的控制向OSD RAM（1a和1b）提供要存储的数据，并且将所存储的数据交替地传送到OSD本地总线12。 屏幕显示单元可以处理高频OSD时钟信号，并正常执行OSD。

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