公开(公告)号：EP0743758A1

公开(公告)日：1996-11-20

申请号：EP95830197.0

申请日：1995-05-15

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Bruccoleri, Melchiorre ,  Demicheli, Marco ,  Patti, Giuseppe ,  Pisati, Valerio

IPC: H03M1/00 ,  G06J1/00 ,  H03M1/78

CPC classification number: H03M1/664 ,  G06J1/00 ,  H03M1/785

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract translation: 由串联的一对线性转换器组成的数字/模拟二次转换器（DACQ）具有第一转换器（DAC1）的输出节点与第二转换器的R-2R型电阻网络的节点的直接耦合（ DAC2）对应于R-2R型电阻网络的LSB级。 高阻抗节点，特别是第二线性转换器的输入节点，有利地从“电流路径”中消除，从而显着地减少了高阻抗节点（具有与其相关的本质上大的寄生电容）的较长建立时间的问题。 二次转换器的独特结构也为电路的显着简化提供了依据。

公开(公告)号：EP0690582B1

公开(公告)日：1996-11-13

申请号：EP94830326.8

申请日：1994-07-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Travaglia, Frederico ,  La Rosa, Maria Grazia ,  Giarrizzo, Guido

IPC: H03L7/10

CPC classification number: H03L7/10

公开(公告)号：EP0740261A1

公开(公告)日：1996-10-30

申请号：EP95830171.5

申请日：1995-04-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruno, Dario ,  Poluzzi, Rinaldo ,  Manaresi, Nicolo ,  Franchi, Eleonora

IPC: G06G7/60 ,  G05F3/24

CPC classification number: G06N7/043 ,  G05F3/24

Abstract: The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form.
It comprises a storage section (MEM) having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals (PP) on such outputs; the storage section (MEM) is input a plurality of supply voltage signals (VI) and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs.
Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches (SW) controlled by storage elements (E) are used in the storage section (MEM).

Abstract translation: 本发明的模拟处理器是可编程的并且能够以模拟形式存储处理系数。 它包括具有至少一个输出的存储部分（MEM），在大多数情况下多个输出，并且适于在这种输出上分别产生编程信号（PP）; 存储部分（MEM）输入多个电源电压信号（VI），并且可操作地结合存储在其中的信息产生每个输出上的电源电压信号中的一个，应当理解，一个电压信号可以 在几个这样的产出上产生。 有利地，如果在存储部分（MEM）中使用由存储元件（E）控制的开关（SW）），则处理器也可以以简单的方式从数字类型的电路编程。

公开(公告)号：EP0740072A1

公开(公告)日：1996-10-30

申请号：EP95830169.9

申请日：1995-04-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Palara, Sergio ,  Di Cicco, Ben, c/o SGS-Thomson Microelectr. Srl

IPC: F02P1/00 ,  F02P17/00 ,  G01R29/027 ,  G01R31/38

CPC classification number: H01T13/60 ,  F02P17/12 ,  G01R29/0273

Abstract: The invention concerns a method of detecting a spark produced by means of a spark coil (L) having a primary circuit (L') connected to a supply voltage generator (Vb) and a secondary circuit (L'') with the spark coil (L) being inserted in an electronic ignition device of an internal combustion motor.
The method consists of the following phases:

generation of a voltage signal (U) proportional to a voltage (VL) present on the primary circuit of the spark coil (L),
comparison of the voltage signal (U) with a first, upper, threshold value (U1) by means of a comparator (C) with hysteresis,
comparison by means of said comparator (C) of the voltage signal (U) with a second, lower, threshold value (U2) proportional to the supply voltage (Vb),
detection of the duration of a voltage (Vc) output from the comparator (C), and
signalling of the presence of the spark if said duration is greater than a reference value (B).

Abstract translation: 本发明涉及一种检测由火花线圈（L）产生的火花的方法，所述火花线圈（L）具有连接到电源电压发生器（Vb）的初级电路（L'）和具有火花线圈的次级电路（L“） L）插入内燃机的电子点火装置中。 该方法包括以下阶段：产生与存在于火花线圈（L）的初级电路上的电压（VL）成比例的电压信号（U），电压信号（U）与第一， 通过具有滞后的比较器（C）的阈值（U1），通过电压信号（U）的所述比较器（C）与与电源电压（Vb）成比例的第二，较低阈值（U2）进行比较 ），检测从比较器（C）输出的电压（Vc）的持续时间，以及如果所述持续时间大于参考值（B）则发出火花的存在。

公开(公告)号：EP0736876A1

公开(公告)日：1996-10-09

申请号：EP95830133.5

申请日：1995-04-04

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/04 ,  G06F11/20

CPC classification number: G11C29/802 ,  G11C16/0433

Abstract: A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected in an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.

Abstract translation: 一种编码设备，包括多位寄存器阵列，每个寄存器由多个可编程非易失性存储单元组成，所述多个可编程非易失性存储单元以OR配置连接到与单个读取电路相关联的寄存器的公共感测线。 第一选择/启用总线（SELbus）控制每个所述可编程存储单元中的每一个与每个多位寄存器的所述公共感测线的连接。 对于第二个配置总线（CODE总线）的每根导线，共同连接与构成每个寄存器的存储单元以及第三个偶然编程总线（PG总线）的每根导线一样多的编程晶体管的电流端子， 连接所述寄存器的相同顺序的存储单元的编程晶体管的栅极。

公开(公告)号：EP0690557B1

公开(公告)日：1996-10-09

申请号：EP94830327.6

申请日：1994-07-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： D'Angelo, Giuseppe ,  Poluzzi, Rinaldo ,  Lo Presti, Matteo

IPC: H02P7/62 ,  G05B13/02 ,  H02P7/628

CPC classification number: H02P27/06 ,  G05B13/0275 ,  H02P23/0004

公开(公告)号：EP0735677A1

公开(公告)日：1996-10-02

申请号：EP95830123.6

申请日：1995-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pulvirenti, Francesco ,  Ursino, Riccardo ,  Gariboldi, Roberto

IPC: H03K3/011 ,  H03K3/0231

CPC classification number: H03K3/011 ,  H03K3/0231 ,  H03K3/354

Abstract: The oscillating circuit in accordance with the present invention comprises a capacitor C, a charge circuitry CCA and a control circuitry CCO. The charge circuitry CCA includes a first GEN1 and a second GEN2 current generators having respectively a first and a second current values and opposite directions and switching means SW1,SW2 designed to couple alternatively the generators GEN1,GEN2 to the capacitor C. The control circuitry CCO has a voltage input coupled to the capacitor C and an output coupled to control inputs of the switching means SW1,SW2 and includes a comparator with hysteresis having a lower threshold and an upper threshold.
If for the difference between the upper threshold and the lower threshold a value is chosen essentially proportional to the ratio of the product to the sum of the two current values the oscillation frequency and the duty cycle depend neither on the supply voltage nor the temperature nor the process.

Abstract translation: 根据本发明的振荡电路包括电容器C，充电电路CCA和控制电路CCO。 充电电路CCA包括分别具有第一和第二电流值和相反方向的第一GEN1和第二GEN2电流发生器，以及设计成将发电机GEN1，GEN2交替耦合到电容器C的开关装置SW1，SW2。控制电路CCO 具有耦合到电容器C的电压输入和耦合到开关装置SW1，SW2的控制输入的输出，并且包括具有较低阈值和较高阈值的滞后的比较器。 如果对于上限阈值和下限阈值之间的差异，则选择一个值基本上与产品与两个电流值之和的比例成比例，振荡频率和占空比既不依赖于电源电压也不依赖于温度， 处理。

公开(公告)号：EP0735542A1

公开(公告)日：1996-10-02

申请号：EP95830127.7

申请日：1995-03-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Telecco, Nicola ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

Abstract: Reading circuit for multilevel non-volatile memory cell devices comprising for each cell to be read a selection line with which is associated a load (ML) and a decoupling and control stage (MF) with a feedback loop (INV) which stabilizes the voltage on a circuit node (F) of the selection line.
To this node are connected the current replica circuit means which are controlled by the feedback loop (INV).
These include loads (M1,M2,M3) and circuit elements (MC1,MC2,MC3) homologous to those associated with the selection line of the memory cell and have output interface circuit means (A,B,C) for connection to current comparator circuit means.

Abstract translation: 用于多电平非易失性存储单元器件的读取电路，包括用于读取与负载（ML）和解耦和控制级（MF）相关联的选择线的每个单元与具有稳定电压的反馈回路（INV） 选择线的电路节点（F）。 该节点连接由反馈回路（INV）控制的当前复制电路装置。 这些包括与存储器单元的选择线相关联的负载（M1，M2，M3）和电路元件（MC1，MC2，MC3），并具有用于连接到电流比较器的输出接口电路装置（A，B，C） 电路方式。

公开(公告)号：EP0734024A1

公开(公告)日：1996-09-25

申请号：EP95830110.3

申请日：1995-03-23

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Telecco, Nicola ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 n (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).

Abstract translation: 一种用于多级存储器单元（MC）的串行二分感测的感测电路，其可以在多个m = 2n（n> = 2）不同编程电平中取一个编程电平，包括用于偏置存储器单元 （MC），以使得存储单元（MC）以具有多个m个不同的单元电流值（IC0-IC3），每个单元电流值（IC0-IC3）的值吸收单元电流（IC） IC0-IC3），用于将电池电流（IC）与可变参考电流发生器（G）产生的参考电流（IR）进行比较的电流比较器（1）和逐次逼近寄存器（ 2）提供电流比较器（1）的输出信号（CMP）并控制可变参考电流发生器（G）。 可变参考电流发生器包括永久地耦合到电流比较器（1）的偏移电流发生器（Ioff）和由逐次逼近寄存器（2）独立激活的m-2个不同的电流发生器（IR0，IR1），每个发生器 等于多个单元电流值（IC0-IC3）中的相应一个的电流（IC1，IC2）。

公开(公告)号：EP0730344A1

公开(公告)日：1996-09-04

申请号：EP95830063.4

申请日：1995-02-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Masini, Marco ,  Baiocchi, Stefania ,  Botti, Edoardo

IPC: H03G1/00 ,  H03F3/217 ,  H03K7/08

CPC classification number: H03F1/083 ,  H03F3/217 ,  H03K7/08

Abstract: A single-pole negative feedback D-class amplifier having first (IN1) and second (IN2) input terminals for coupling to a signal source and an output terminal (OUT) through which it transfers the pulse modulated signals to a demodulating filter.
A first resistor (R1) is feedback connected between the output terminal and an input circuit node (N) connected to the second input terminal.
A second resistor (R2) is connected between that node (N) and the second input terminal (IN2).
A capacitor is connected between the circuit node (N) and the first input terminal (IN1).

Abstract translation: 具有用于耦合到信号源和输出端（OUT）的第一（IN1）和第二（IN2）输入端的单极性负反馈D级放大器，通过它们将脉冲调制信号传送到解调滤波器。 第一电阻器（R1）反馈连接在输出端子和连接到第二输入端子的输入电路节点（N）之间。 第二电阻器（R2）连接在该节点（N）和第二输入端子（IN2）之间。 电容器连接在电路节点（N）和第一输入端（IN1）之间。