公开(公告)号：JP2009124178A

公开(公告)日：2009-06-04

申请号：JP2009042807

申请日：2009-02-25

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： EGUCHI KOHEI ,  MIZUO YUURI

IPC: H01L21/76 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has a trench-type element separation structure with improved electric characteristics, and to provide its manufacturing method.
SOLUTION: A groove 4 is covered with a first silicon oxide film 6 and heated. A joint 7 formed on the first silicon oxide film 6 is covered with a second silicon oxide film 8 and heated again. Thus, the first silicon oxide film 6 and the second silicon oxide film 8 are made to be high in density, and the groove 4 is covered with them as a rigid element isolation oxide film 9 with an uniform etching rate.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改善的电特性的沟槽型元件分离结构的半导体器件，并提供其制造方法。 解决方案：槽4被第一氧化硅膜6覆盖并加热。 形成在第一氧化硅膜6上的接头7被第二氧化硅膜8覆盖并再次加热。 因此，第一氧化硅膜6和第二氧化硅膜8的密度高，槽4被作为刚性元件隔离氧化膜9以均匀的蚀刻速率被覆盖。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008193038A

公开(公告)日：2008-08-21

申请号：JP2007099820

申请日：2007-04-05

Applicant: United Microelectronics Corp ,  聯華電子股▲分▼有限公司

Inventor： CHEN MEI-LING ,  LAI KUO-CHIH ,  SUNG SU-JEN ,  HUANG CHEN-CHUNG ,  LAI YU-TSUNG

IPC: H01L21/768 ,  C23C16/40 ,  C23C16/455 ,  H01L21/316 ,  H01L23/522

CPC classification number: H01L21/31695 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/7682 ,  H01L21/76835 ,  Y10T428/24992

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a porous low-permittivity layer. SOLUTION: A CVD process is introduced to a substrate to which a frame precursor and a porogen precursor are supplied. In the supply stop period of the frame precursor, the value of at least one deposition parameter which is negatively correlated with the density of a product of the CVD process decreases. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供形成多孔低介电常数层的方法。 解决方案：将CVD工艺引入到其中提供框架前体和致孔剂前体的基底上。 在框架前体的供给停止期间，与CVD工序的产品的密度呈负相关的至少一个沉积参数的值降低。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007328015A

公开(公告)日：2007-12-20

申请号：JP2006157196

申请日：2006-06-06

Applicant: United Microdisplay Optronics Corp ,  United Microelectronics Corp ,  聯華電子股▲分▼有限公司 ,  聯誠光電股▲フン▼有限公司

Inventor： SHU SHIKEN ,  O FUKOKU ,  GO GITEI

IPC: G02F1/1337

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a liquid crystal alignment layer by which powders and particles are prevented from producing on an organic alignment layer and a patterning process can be conducted on an inorganic alignment layer so as to increase the latitude of design of the inorganic alignment layer. SOLUTION: The method for manufacturing the liquid crystal alignment layer includes a step to conduct an ion implantation process after furnishing a step to provide an organic or inorganic material layer on a substrate for the purpose of imparting alignment treatment to the organic or inorganic material layer. As the alignment treatment is a kind of noncontact method, it reduces probability of damaging the organic alignment layer so as to prevent the production of powder and particles. Furthermore, the inorganic material layer is formed on the substrate before the alignment treatment, and thereby the inorganic material layer is pattern formed before the alignment treatment. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决问题的方案：提供一种制造液晶取向层的方法，通过该方法可以防止在有机取向层上产生粉末和颗粒，并且可以对无机取向层进行图案化处理，以增加 无机取向层设计的纬度。 解决方案：液晶取向层的制造方法包括在提供在基材上提供有机或无机材料层的步骤之后进行离子注入工艺的步骤，用于赋予有机或无机的取向处理 材料层。 由于取向处理是一种非接触方法，因此降低了有机取向层损伤的可能性，从而防止粉末和颗粒的产生。 此外，在取向处理之前，在基板上形成无机材料层，从而在取向处理之前形成无机材料层。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007319695A

公开(公告)日：2007-12-13

申请号：JP2007177646

申请日：2007-07-05

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： HAZAMA KATSUKI

IPC: A63F1/18 ,  A63F1/02 ,  A63F1/06 ,  A63F3/00 ,  A63F3/02 ,  G06K17/00 ,  G06K19/00 ,  G06K19/07

Abstract: PROBLEM TO BE SOLVED: To provide a data carrier which can correctly recognize a position relation of surface/backside judgement by a card reader side and independently have a first function corresponding to the surface side of a card and a second function corresponding to the backside individually. SOLUTION: A non-contact type data carrier 1 receives radio waves 20 transmitted from a card reader 1 by an antenna and an information communication part to acquire required power and information. Required processing is carried out by a control part based on the acquired information and information stored in a multi-value memory. By a surface/backside judging part, surface or backside of the data carrier 1 is detected based on the direction of electric current flowing in a coil L. Based on the detection result, different functions are carried out. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种数据载体，其能够正确地识别读卡器侧的表面/背面判断的位置关系，并且独立地具有对应于卡的表面侧的第一功能和对应于 背面单独。 解决方案：非接触型数据载体1通过天线和信息通信部分接收从读卡器1发送的无线电波20以获取所需的功率和信息。 基于所获取的信息和存储在多值存储器中的信息，由控制部分执行所需的处理。 通过表面/背面判断部分，基于在线圈L中流动的电流的方向来检测数据载体1的表面或背面。基于检测结果，执行不同的功能。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP3697358B2

公开(公告)日：2005-09-21

申请号：JP32480798

申请日：1998-11-16

Applicant: ユナイテッド マイクロエレクトロニクス コープUnited Microelectronics Corp.

Inventor： 永 昌 林 ,  士 毅 陳 ,  東 波 陳

IPC: H01L21/822 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10

公开(公告)号：JP3672760B2

公开(公告)日：2005-07-20

申请号：JP3925599

申请日：1999-02-17

Applicant: ユナイテッド マイクロエレクトロニクス コープUnited Microelectronics Corp.

Inventor： 俊 元 ▲呉▼ ,  昭 元 ▲黄▼ ,  火 鐵 盧

IPC: H01L21/3205 ,  H01L21/304

公开(公告)号：JP2005117011A

公开(公告)日：2005-04-28

申请号：JP2004164221

申请日：2004-06-02

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： YU KOKUSHU ,  KAN DAISO ,  CHIN SEIRYU ,  CHANG YI-MING

IPC: H01L23/12 ,  H01L21/76

CPC classification number: H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for a wafer level package. SOLUTION: A plurality of spacer wall structures are formed in a semiconductor wafer or a light transmitting substrate, and the position of a sealant is precisely controlled by the formation of the plurality of spacer wall structures. An element size is determined by positions of a spacer wall and the sealant. Thereby, the distance between the sealant and a photosensitive region is shortened to carry out processes of completing the package of the wafer and scribing. After that, an increase in the number of dies is achieved, and its production capacity is enhanced. In addition to this, the height of the spacer wall is controlled by a semiconductor process, and the uniformity of the gap between the semiconductor wafer and the light transmitting substrate and the stability of the width of the sealant are controlled to enhance its yield. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供晶片级封装的方法和结构。 解决方案：在半导体晶片或透光基板中形成多个间隔壁结构，通过形成多个间隔壁结构来精确地控制密封剂的位置。 元件尺寸由间隔壁和密封剂的位置决定。 由此，缩短了密封剂与感光区域之间的距离，进行了完成晶圆封装和划线的工序。 之后，实现了模具数量的增加，生产能力得到提高。 除此之外，通过半导体工艺控制间隔壁的高度，并且控制半导体晶片和透光基板之间的间隙的均匀性以及密封剂的宽度的稳定性，以提高其产量。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003249555A

公开(公告)日：2003-09-05

申请号：JP2002041178

申请日：2002-02-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SEIYU ,  KA SOGI

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a bar circuit which reduces crosstalks and eddy currents in an integrated circuit. SOLUTION: The bar circuit comprises a first conductivity semiconductor substrate, a second conductivity first elongate well in the semiconductor substrate, and a second conductivity second elongated well in the semiconductor substrate. The second elongated well is under the first elongate well and adjacent to under the first elongated well, thereby connecting it with a barrier to cut off the crosstalks and eddy currents. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002231693A

公开(公告)日：2002-08-16

申请号：JP2001042912

申请日：2001-02-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YU CHIA-CHIEH

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a photolithographic and etching method for simplifying process by forming a conductive layer, having a large critical width in situ and forming a shallow trench isolation structure, in which the conductive layer having the larger critical width can be formed on a device having a large step. SOLUTION: In the photolithographic and etching method, a substrate having a conductive layer, a first mask layer and a second mask layer are formed sequentially as the conductive layer, and a patterned photoresist layer is formed on the substrate; with the mask of the photoresist layer, part of the second mask layer is removed to form a second mask layer, having a narrow upper part and a wide bottom part in the side face on the first mask layer; with the mask of the second mask layer, a part of the first mask layer is removed, and the photoresist layer is removed and using the mask of the first mask layer, part of the second mask layer and the conductive layer is removed to form a conductive pattern on the substrate; and finally the first mask layer is removed.

公开(公告)号：JP2002231598A

公开(公告)日：2002-08-16

申请号：JP2001007819

申请日：2001-01-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YU CHIA-CHIEH

IPC: G03F7/11 ,  G03F7/42 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide the method of reprocessing photoresist layers for preventing reflection prevention capability from being reduced in an oxysilicon nitride layer. SOLUTION: A silicon chip is provided, where the silicon chip has an insulating layer, bottom-section reflection prevention coating, and the photoresist layer on the coating. The photoresist layer has already been exposed and developed. To remove the greater part of the photoresist layer, wet etching work is carried out. To remove a cured residual photoresist material, low-temperature plasma treatment is executed, where the low-temperature plasma treatment prevents a change in the structure of reflection prevention coating. A new photoresist layer is formed on a bottom-section reflection prevention coating.