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公开(公告)号：KR1020160126290A
公开(公告)日：2016-11-02
申请号：KR1020150057191
申请日：2015-04-23
Applicant: 삼성전기주식회사
CPC classification number: H01L21/288 , H01L21/4857 , H01L21/486 , H01L21/6835 , H01L23/49822 , H01L23/49827 , H01L2221/68345 , H01L2224/16225 , H05K1/113 , H05K1/141 , H05K2201/049 , H05K2201/09036 , H05K2201/09472 , H05K2201/10242 , H05K2201/10378
Abstract: 본발명에따른인쇄회로기판은, 절연층; 상기절연층의하면에형성된회로층; 상기회로층과연결되며, 상기절연층의하면에서상면으로연장되어형성된금속포스트를포함하여구성된다. 본발명의인쇄회로기판은다이와의연결을위한금속포스트를높이공차를확보하고기판내에함몰된구조로형성함으로써소자실장시 솔더브릿지에의한쇼트발생을방지할수 있다.
Abstract translation: 公开了一种印刷电路板，其包括绝缘层，形成在绝缘层的下表面上的电路层和接触电路层并从绝缘层的下表面延伸到上表面的金属柱。 印刷电路板能够通过形成金属柱来安装元件以防止短路，以具有固定的高度公差以与模具连接并且将其形成为凹陷形状。
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公开(公告)号：KR101514485B1
公开(公告)日：2015-04-22
申请号：KR1020110068949
申请日：2011-07-12
Applicant: 삼성전기주식회사
Abstract: 본 발명은 2단으로 적층된 캐리어층, 각 캐리어층의 노출된 면에 각각 적층된 시드층, 각 캐리어층 및 각 시드층의 외곽을 둘러싸는 절연층 및 절연층의 양면에 각각 도포된 금속층을 포함하는 기판 제조용 캐리어로 접착제 없이 중심에 있는 캐리어층 및 시드층의 외곽을 절연재로 감싸 고정하는 방식의 기판 제조용 캐리어를 사용하여 두 개의 코어리스 기판을 용이하게 제조할 수 있다.
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公开(公告)号：KR1020140030918A
公开(公告)日：2014-03-12
申请号：KR1020120097683
申请日：2012-09-04
Applicant: 삼성전기주식회사
CPC classification number: H05K1/0201 , H05K1/09 , H05K3/0035 , H05K3/4644 , H05K2201/0338 , H05K2201/0341
Abstract: The printed circuit board relates to a printed circuit board. To remove the penetration risk of a circuit layer in a laser emitting process, provided is the printed circuit board which includes: an insulation layer; the circuit layer which is formed on one side of the insulation layer; and a via electrode which passes through the insulation layer and is in contact with the circuit layer. The circuit layer is formed by laminating the heterogeneous metal layers with different thermal conductivities.
Abstract translation: 印刷电路板涉及印刷电路板。 为了消除激光发射过程中的电路层的穿透风险，提供了印刷电路板，其包括：绝缘层; 所述电路层形成在所述绝缘层的一侧上; 以及通过绝缘层并与电路层接触的通孔电极。 电路层通过层叠具有不同热导率的非均相金属层而形成。
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公开(公告)号：KR1020140021910A
公开(公告)日：2014-02-21
申请号：KR1020120088424
申请日：2012-08-13
Applicant: 삼성전기주식회사
CPC classification number: H05K1/0204 , H01L24/19 , H01L2224/04105 , H01L2224/73267 , H05K1/0271 , H05K1/185 , H05K3/4608 , H05K2201/09681
Abstract: A core substrate according to the embodiment of the present invention includes one or more connection members, a heat radiation member which is located near the connection member and is divided into a plurality of parts, and an insulation member which is formed between the heat radiation members which are divided into the parts and between the connection member and the heat radiation member.
Abstract translation: 根据本发明的实施例的芯基板包括一个或多个连接构件，位于连接构件附近并被分成多个部分的散热构件和形成在散热构件之间的绝缘构件 其被分成部分和连接构件和散热构件之间。
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公开(公告)号：KR1020130065216A
公开(公告)日：2013-06-19
申请号：KR1020110131972
申请日：2011-12-09
Applicant: 삼성전기주식회사
CPC classification number: H05K3/06 , H05K1/0203 , H05K1/0298 , H05K1/116 , H05K3/4652 , H05K3/4682 , H05K2201/09736 , H05K2203/0369 , H05K2203/1476
Abstract: PURPOSE: A multi-layered printed circuit board and a manufacturing method thereof are provided to prevent generation of void as being able to be manufactured in thin thickness. CONSTITUTION: A multi-layered printed circuit board includes an insulating layer(120), an inner layer pad(131), an inner layer circuit line(133), a via(163) and an outer layer circuit line(165). The insulating layer is formed by dipping a fiber to an epoxy. The inner layer pad and the inner layer circuit line are arranged in the insulating layer. Thickness(H2) of the inner layer circuit line is thinner than thickness(H1) of the inner layer pad. The via passes through the insulating layer and is connected to the inner layer pad. The outer layer circuit line is formed on the outer surface of the insulating layer, by performing plating on a via hole(151) and the insulating layer and then etching a plated layer.
Abstract translation: 目的：提供一种多层印刷电路板及其制造方法，以防止能够以薄的厚度制造空隙。 构成：多层印刷电路板包括绝缘层（120），内层焊盘（131），内层电路线（133），通孔（163）和外层电路线（165）。 通过将纤维浸渍到环氧树脂中而形成绝缘层。 内层焊盘和内层电路线布置在绝缘层中。 内层电路线的厚度（H2）比内层衬垫的厚度（H1）薄。 通孔穿过绝缘层并连接到内层垫。 通过在通孔（151）和绝缘层上进行电镀，然后对镀层进行蚀刻，在绝缘层的外表面上形成外层电路线。
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Patent Agency Ranking
公开(公告)号：KR1020130030555A
公开(公告)日：2013-03-27
申请号：KR1020110094112
申请日：2011-09-19
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A laminated plate for a printed circuit board and a manufacturing method of a printed circuit board are provided to reduce manufacturing time and cost by inserting an electronic device without forming a cavity in an insulator. CONSTITUTION: An electronic device is tack-welded to one side of an insulator of semi-hardened state(S210). The electronic device is inserted into the insulator. By the insertion, the electronic device is pressurized. A carrier is disposed on both sides of the insulator(S220). The carrier is pressurized and removed. [Reference numerals] (AA) Step of disposing a carrier, in which a conductive layer is laminated on one side thereof, on both sides of the insulator and pressurizing the carrier; (BB) Step of hardening the insulator to integrate the conductive layer and the insulator; (CC) Step of removing the carrier; (S210) Step of tack-welding an electronic device to one side of a semi-hardened insulator; (S220) Step of pressurizing the electronic device to prepare a laminate plate for a printed circuit board in which the electronic device is inserted in the insulator; (S230) Step of forming a circuit pattern which is electrically connected to the electronic device on the conductive layer
Abstract translation: 目的：提供一种用于印刷电路板的层叠板和印刷电路板的制造方法，以通过插入电子器件而不在绝缘体中形成空腔来减少制造时间和成本。 构成：将电子装置固定在半硬化状态的绝缘体的一侧（S210）。 电子设备插入绝缘体。 通过插入，电子设备被加压。 载体设置在绝缘体的两侧（S220）。 载体被加压和移除。 （附图标记）（AA）在绝缘体的两侧设置在其一侧层叠有导电层并对载体加压的载体的工序; （BB）使绝缘体硬化以使导电层和绝缘体整合的步骤; （CC）拆卸承运人的步骤; （S210）将电子器件定位于半硬化绝缘子的一侧的步骤; （S220）对电子设备进行加压以制备其中电子器件插入绝缘体中的印刷电路板的叠层板的步骤; （S230）形成与导电层上的电子器件电连接的电路图形的工序
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公开(公告)号：KR1020130026750A
公开(公告)日：2013-03-14
申请号：KR1020110090113
申请日：2011-09-06
Applicant: 삼성전기주식회사
CPC classification number: H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: PURPOSE: An interposer substrate, a semiconductor package, and a manufacturing method thereof are provided to reduce manufacturing costs by cutting a plurality of pattern arrays into units when the interposer substrate is applied to the semiconductor package. CONSTITUTION: An interposer substrate(100) is formed between a first package and a second package. The interposer substrate includes a plurality of pattern arrays(120a-120e) with a base substrate(110) and a circuit pattern(120) which are arranged in a row. The base substrate is made of insulation materials. The plurality of pattern arrays are separately arranged. A first semiconductor device is formed on one side of the first package. A second semiconductor device is formed on one side of the second package.
Abstract translation: 目的：提供一种内插衬底，半导体封装及其制造方法，以在将内插衬底施加到半导体封装件时将多个图案阵列切割成单元来降低制造成本。 构成：在第一封装和第二封装之间形成插入器基板（100）。 插入器基板包括具有基底基板（110）和排列成一排的电路图案（120）的多个图案阵列（120a-120e）。 基底由绝缘材料制成。 多个图案阵列分开设置。 第一半导体器件形成在第一封装的一侧上。 第二半导体器件形成在第二封装的一侧上。
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公开(公告)号：KR101156854B1
公开(公告)日：2012-06-20
申请号：KR1020100068104
申请日：2010-07-14
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
Abstract: 본 발명은 반도체 패키지 기판 및 그 제조방법에 관한 것으로, 본 발명의 패키지 기판은 전자 부품 실장 면에만 접속 패드를 포함하는 회로 패턴을 구비한 단면 기판 구조로서, 비아홀의 내벽에 형성된 금속 도금층과 비아홀 내부에 충전된 도전성 금속 페이스트로 이루어진 접속 비아를 통해서 상면의 접속 패드와 하면의 외부접속 단자를 직접 연결할 수 있다.
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99.发明公开
公开(公告)号：KR1020120063606A
公开(公告)日：2012-06-18
申请号：KR1020100124637
申请日：2010-12-08
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A via structure, a method for forming thereof, a circuit board having the same, and a method for manufacturing thereof are provided to produce fine pitch by reducing an occupied area of conductive via. CONSTITUTION: A base substrate(110) has an internal circuit pattern. The base substrate comprises a core layer(112) consisting of resinous material. An insulating layer(120) covers the base substrate. An external circuit pattern covers the insulating layer. A via hole(127) passes through the base substrate and the insulating layer. Conductive via(140) is included within the via hole. One end of the conductive via is connected with the internal circuit pattern and the other end of the conductive via is connected with the external circuit pattern.
Abstract translation: 目的：提供通孔结构，其形成方法，具有该通孔结构的电路板及其制造方法，以通过减小导电通孔的占用面积来产生细间距。 构成：基底（110）具有内部电路图案。 基底包括由树脂材料构成的芯层（112）。 绝缘层（120）覆盖基底。 外部电路图案覆盖绝缘层。 通孔（127）穿过基底基板和绝缘层。 导电孔（140）包括在通孔内。 导电通孔的一端与内部电路图形连接，导电通孔的另一端与外部电路图形连接。
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公开(公告)号：KR101117155B1
公开(公告)日：2012-03-07
申请号：KR1020100063595
申请日：2010-07-01
Applicant: 삼성전기주식회사
CPC classification number: H01L23/3121 , H01L21/56 , H01L23/49827 , H01L23/5389 , H01L2224/04105 , H01L2224/73267 , H01L2224/92244 , H01L2924/15153
Abstract: 임베디드기판제조방법이개시된다. 상기임베디드기판제조방법은양면에패턴이형성되고상하부가관통되는캐비티가형성되는코어기판; 상기캐비티에내장되는칩; 및상기패턴을보호하도록상기코어기판의양면에각각구비되는제1, 제2 절연체를포함하는임베디드기판제조방법에있어서, 상기코어기판을준비하는단계; 상기캐비티의하측을차폐하도록상기코어기판의하면에상기제1 절연체를라미네이션하는단계; 상기캐비티로노출되는상기제1 절연체에접착층을형성하는단계; 상기접착층에상기칩을접착시켜, 상기캐비티에상기칩을내장하는단계; 및상기코어기판의상면에상기제2 절연체를라미네이션하는단계를포함한다.
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