Abstract:
PURPOSE: An adaptive interference mitigating receiver for a DS/CDMA communication system using space-time block coding is provided for a quality service at a high speed by improving data detection performance in a multi-path fading channel environment. CONSTITUTION: Chip matching filters(210,220) match-filter signals received from antennas(40) on the basis of a chip period and output them. Input signal generation buffers(310,320) generate vectors corresponding to signal blocks outputted from the chip matching filters(210,220) and output them according to a symbol period. Adaptive filter blocks(410-440) filter signals outputted from the input signal generation buffers(310,320) according to a tab weight controlled by a specific period and output them. A coupler(600) couples the signals outputted from the adaptive filter blocks(410-440) and outputs it. A data determining unit(700) restores an original signal that a specific user intends to transmit by using a signal outputted by the coupler(600). A reference signal selector(800) selectively outputs either a signal outputted from the data determining unit(700) or a learn data signal. Error generation blocks(510-540) generate an error signal for controlling a tap weight used in the adaptive filter blocks(410-440) by using a signal outputted from the reference signal selector(800) and a signal outputted from the adaptive filter blocks(410-440).
Abstract:
PURPOSE: An add-compare-select(ACS) and trellis-coded-modulation decoder using the acs are provided to prevent an overflow phenomenon due to cumulation of path metric values and estimate a channel state and a bit error rate by using the normalization function and the error monitoring function. CONSTITUTION: An adder(122) adds a cumulative path metric value of a current state to a branch metric value. A minimum value table(121) is used for storing a cumulative path metric minimum value. A subtracter(123) is used for subtracting an output value of the minimum value table(121) from an output value of the adder(122). A selector(124) selects one from an output value of the subtracter(123) and the output value of the adder(122). A comparator(125) is used for comparing a selected value of the selector(124) with a cumulative path metric value of the next state of the second survival path metric memory portion. A selector(126) outputs the selected value of the selector(124) and a smaller value of the cumulative path metric values of the next state to the cumulative path metric value of the next state.
Abstract:
본 발명은 512포인트 FFT 회로를 구현하는데 있어서 512포인트 FFT 회로는 제 1단계의 64포인트 FFT 와 제 2단계의8포인트 FFT로 분할되어 구성되며, 제 1단계의 64포인트 FFT는 2 개의 8포인트 FFT로 분할되어 구성되고, 이 때 제 1단계의 64포인트 FFT와 제 2단계의 8포인트 FFT사이에서 제 1단계의 64포인트 FFT에서 행 단위로 출력되는 변환의 결과를 저장하며, 저장된 행 단위 변환의 결과를 열 단위로 제 2단계의 8포인트 FFT에 공급하는 기능을 수행하는 셔플메모리 SM2, 최초 입력 샘플을 행 단위로 저장하고 동시에 제 1단계의 64포인트 FFT에 열 단위로 데이터를 공급하는 셔플메모리 SM1, 제 2단계의 8포인트 FFT의 출력을 행 단위로 저장하고 동시에 열 단위로 512포인트 FFT의 최종 결과를 출력하는 셔플메모리 SM3로 구성되는 고성능 512포인트 FFT회로에 관한 것이다.