公开(公告)号：JPS6073718A

公开(公告)日：1985-04-25

申请号：JP18113183

申请日：1983-09-29

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI ,  NAKAHARA YASUHIRO ,  NEGISHI HITOSHI ,  NAKAMURA OSAMU

IPC: H02J1/00 ,  G06F1/00 ,  G06F1/26 ,  G06F3/00

Abstract: PURPOSE:To perform power supply to an input-output device installed to a remote place from the main body of an electronic computer, by installing a no- break power supplying means, such as a battery, etc., to the connecting device of optical fibers. CONSTITUTION:The main body 1 of an electronic computer is connected to a connecting device 6 through another connecting device 4 and an optical fiber transmission line 5. Only a circuit of the connecting device 6 which receives signals from the transmission line 5 and detects whether an optical signal exists or not, is always set to an operable condition by means of a battery 7. If the connecting device 6 detects an optical signal coming from the transmission line 5 when input-output devices 8a-8n and the connecting device 6 are set to a condition where the AC power supply is cut off, the connecting device 6 performs its own AC power supply and succeedingly issues a turning-on command of AC power supply to the input/output devices 8a-8n. Therefore, power supply to an input/output device installed to a remote place from the main body of an electronic computer can be performed.

公开(公告)号：JPS6072441A

公开(公告)日：1985-04-24

申请号：JP18112883

申请日：1983-09-29

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI ,  NAKAHARA YASUHIRO ,  NEGISHI HITOSHI ,  NAKAMURA OSAMU

IPC: H04L12/437

Abstract: PURPOSE:To attain ease of troubleshooting of a failed part by transmitting a data transmission line of a spare system to transmit a diagnostic data from a highway supervising node and demarcating a failed part with reflected data supplied from a station node at which an existing system transmission line is by- passed. CONSTITUTION:When a fault notice is received from a station node A, a highway supervising node B uses a data frame, transmits a by-pass command to the node A, which is brought to the by-pass state at a relay section 33 of the existing system. The node B transmits the diagnostic data to the spare system data transmission line side by the control of a microprocessor section 62 toward the node A. When the node A receives the said diagnostic data, a diagnostic control section 47 performs reflected control according to the reflected condition added to the diagnostic data and transmits a diagnostic response data to the node B. The node B compares the response data supplied from the node A with the transmitted diagnostic data to find out a failed part of the node A.

公开(公告)号：JPS6046637A

公开(公告)日：1985-03-13

申请号：JP15469983

申请日：1983-08-24

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI ,  NAKAHARA YASUHIRO ,  NAKAMURA OSAMU ,  NEGISHI HITOSHI

IPC: H04L12/26

Abstract: PURPOSE:To diagonize a test pattern in every fixed period without exerting influence upon other communication and to attain preventive maintenance by sending the test pattern only in a previously specified time slot. CONSTITUTION:A monitoring node 21 and station nodes 22, 23 are connected through a ring-like transmission line 24 and data are transmitted/received by a frame including time slots. Control bit parts CTL 0, 1 are formed in the time slots TS#0-n and indicate normal data transfer when a bit CTL0 is ''0'' and a diagnosis mode in case of ''1''. An interval timer (not shown) generates an interruption to input a test pattern to an FIFO1, so that the CTL0 of the time slot on the corresponding part is turned on, the test pattern is sent, the returned data are stored in an FIFO2, and both the FIFOs are compared to diagnoze the corresponding part.

公开(公告)号：JPS5953587B2

公开(公告)日：1984-12-26

申请号：JP4179779

申请日：1979-04-06

Applicant: FUJITSU LTD

Inventor： SATO MASAO ,  MITA TERUYOSHI ,  HOSHI FUMIO

IPC: G06F12/16 ,  G06F12/06 ,  G06F13/00 ,  G11C7/00

公开(公告)号：JPS59119935A

公开(公告)日：1984-07-11

申请号：JP23262882

申请日：1982-12-25

Applicant: FUJITSU LTD

Inventor： TAKEYAMA AKIRA ,  TAZAKI TAKASHI ,  NOJIMA SATOSHI ,  MITA TERUYOSHI

IPC: H04B10/035 ,  H04B10/07 ,  H04B10/079 ,  H04B10/275 ,  H04B10/29 ,  H04B17/40 ,  H04L25/02

Abstract: PURPOSE:To separate a faulted section and to recover a fault by using ON or OFF continuous signals of the optical signal to inform a break or fault of an input optical signal to the adjacent optical repeaters. CONSTITUTION:A type always having ON/OFF variations within a certain fixed time is used for the signal on a transmission line. Both a clock and a level can be normally detected when the transmission line and a repeater of the preceding stage are normal. In case the transmission line is disconnected (shown by a mark x), both the clock and the level are cut off and faulted respectively. If such the erroneous clock and level are repeated as they are, all repeaters (Rep1, Rep2...) at and after the faulty section are made faulty. Thus it is impossible to specify a fault section. Therefore an ON signal of light is transferred in place of the direct relay of such an error. Accordingly, the light level is normal in the normal sections of the transmission line, the disconnection of transmission line can be discriminated at least within a system although in the line between the in-use stage and the preceding stage is normal, since a clock error is detected.

公开(公告)号：JPS59101946A

公开(公告)日：1984-06-12

申请号：JP21188082

申请日：1982-12-02

Applicant: Fujitsu Ltd

Inventor： NEGISHI HITOSHI ,  KITANO YOSHIHIRO ,  MITA TERUYOSHI

IPC: H04L12/42

CPC classification number: H04L12/42

Abstract: PURPOSE:To control the priority order of a subsystem whose communication quantity is large, by adding only a few circuits, and to shorten a waiting time of an idle packet, by determining the priority order of each subsystem by a monitoring device. CONSTITUTION:A monitoring device is provided on an annular data highway system, data from a transmission line 1 is separated into a data component and a clock component by a repeater 25 of its monitoring device, and the data component is converted to parallel data by a register 26 and is inputted to a frame buffer memory 31. Also, a timing clock is generated by a timing generating circuit 28 for inputting a timing component, a synchronizing flag of a frame header is detected by a data synchronization detecting circuit 27, and outputs of the circuits 27, 28 are provided to a common controlling circuit 30. A timing signal from this circuit 30 is applied to the memory 31, a transmitting buffer 32 and a priority order determining part 33. Subsequently, the priority order is determined in accordance with algorithm for determining the order in the determining part 33, an address is informed to the buffer 32, and the priority order of the system is controlled.

Abstract translation: 目的：通过监控设备来确定每个子系统的优先顺序，来控制通信量大的子系统的优先级顺序，仅添加少量电路，缩短空闲分组的等待时间。 构成：在环形数据高速公路系统上设置监视装置，通过其监视装置的中继器25将来自传输线路1的数据分离为数据部件和时钟部件，并将数据部件通过 寄存器26输入到帧缓冲存储器31.此外，定时时钟由定时产生电路28产生，用于输入定时分量，由数据同步检测电路27检测帧头的同步标志，并输出 将电路27,28提供给公共控制电路30.来自该电路30的定时信号被施加到存储器31，发送缓冲器32和优先顺序确定部分33.随后，根据 利用用于确定确定部分33中的顺序的算法，将地址通知给缓冲器32，并且控制系统的优先顺序。

公开(公告)号：JPS5950645A

公开(公告)日：1984-03-23

申请号：JP16130282

申请日：1982-09-16

Applicant: Fujitsu Ltd

Inventor： TAZAKI TAKASHI ,  TAKEYAMA AKIRA ,  NOJIMA SATOSHI ,  MITA TERUYOSHI ,  YATSUHOSHI AKIMASA

IPC: H04L25/40 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0337

Abstract: PURPOSE:To synchronize with a clock, by comparing a phase between an input data train and a clock signal, and delaying the input data train when the difference is large. CONSTITUTION:The phase difference between the input data train Di1 and the clock signal CK is detected at a phase selecting circuit PSEL. When the phase difference between the input data train Di1 and the clock signal CK is smaller than a half the period of the clock signal, the input data train Di1 is fed to a waveform shaping circuit SHP by controlling a switch SW. When the phase difference of the both is larger than a half the period of the clock signal, the input data train Di1 is fed to the waveform shaping circuit SHP via a delay circuit DLY. The delay circuit DLY delays an input signal by a half the period of the clock signal. The data reproduction and shaping are attained without using an extracted clock from the input data.

Abstract translation: 目的：与时钟同步，通过比较输入数据串和时钟信号之间的相位，并在差异较大时延迟输入数据序列。 构成：在相位选择电路PSEL中检测输入数据串Di1与时钟信号CK之间的相位差。 当输入数据串Di1和时钟信号CK之间的相位差小于时钟信号周期的一半时，通过控制开关SW将输入数据串Di1馈送到波形整形电路SHP。 当两者的相位差大于时钟信号的周期的一半时，输入数据串Di1经由延迟电路DLY馈送到波形整形电路SHP。 延迟电路DLY将输入信号延迟时钟信号的一半周期。 在不使用从输入数据提取的时钟的情况下获得数据再现和整形。

公开(公告)号：JPS5940739A

公开(公告)日：1984-03-06

申请号：JP15048082

申请日：1982-08-30

Applicant: Fujitsu Ltd

Inventor： TAKEYAMA AKIRA ,  TAZAKI TAKASHI ,  NOJIMA SATOSHI ,  ARITAKA TOKUHIRO ,  MITA TERUYOSHI

IPC: H04J3/08 ,  H04B1/74 ,  H04B3/46 ,  H04L1/24 ,  H04L12/437

CPC classification number: H04B1/745 ,  H04L1/243 ,  H04L12/437

Abstract: PURPOSE: To form a loopback in a short time at the generation of a failure, by using a control circuit of each node closing a connecting path in response to the first connecting path closing signal from a centralized monitor, and operating according to the next opening switch in response to a signal at a receiving end and the presence of an input error of a transmission line of the side node.
CONSTITUTION: The information from the systems 0 and passes through a transmission line switching circuit TLC respectively va a receiving section RV, a level reproducing circuit LV, and a clock synchronism circuit CSC in a node control circuit, the required information is fetched, transmitted from a transmission section DV to the opposite node. A command from the centralized monitor is received at a command receiving circuit CMR, where each command is stored and tansmitted to a loopback control circuit LBC. The control circuit LBC utilizes logic between error signals 0/1 inputted from the circuit LV of each system and the synchronism circuit CSL and the received command, and the loopback signal 0/1 controlling the switching circuit TLC is transmitted to the switching circuit TLC.
COPYRIGHT: (C)1984,JPO&Japio

Abstract translation: 目的：为了在产生故障的短时间内形成环回，通过使用响应于来自集中式监视器的第一连接路径关闭信号关闭连接路径的每个节点的控制电路，并根据下一个开启 响应于接收端的信号而切换并存在侧节点的传输线的输入错误。 构成：来自系统0的信息分别通过传输线路切换电路TLC和节点控制电路中的接收部分RV，电平再现电路LV和时钟同步电路CSC，所需的信息被取出，从 传输部分DV到相对的节点。 在命令接收电路CMR处接收来自集中监视器的命令，其中每个命令被存储并传送到环回控制电路LBC。 控制电路LBC利用从每个系统的电路LV输入的误差信号0/1与同步电路CSL和接收到的命令之间的逻辑，并且控制开关电路TLC的回送信号0/1被发送到开关电路TLC。

公开(公告)号：JPS594366A

公开(公告)日：1984-01-11

申请号：JP11326182

申请日：1982-06-30

Applicant: Fujitsu Ltd

Inventor： TAZAKI TAKASHI ,  TAKEYAMA AKIRA ,  NOJIMA SATOSHI ,  MITA TERUYOSHI

IPC: H03M5/04 ,  H04L25/24 ,  H04L25/49 ,  H04L25/52

CPC classification number: H04L25/242

Abstract: PURPOSE:To eliminate the need for analog components, by storing the transition signal of data in response to the phase difference between an own clock and a clock of a receiving signal and comparing the storage content and the data transition obtained from the receiving signal. CONSTITUTION:A signal is shifted by flip-flops 20-25 and stored once in a flip- flop 28 and written in an ROM26 in response to an output clock (f) of a frequency divider 29. The ROM26 references a table written in advance with an input data and generates an output data. A flip-flop 27 latches an output data Qn and an output data Qn-1 before one clock, outputs the data Qn to an optical LSI link transmitter 30 in response to the clock of the frequency divider 29 and feeds back the data Qn-1, Qn and the data of phase difference provided for the data Qn-1, Qn to the ROM26. The ROM26 discriminates the bit error from the data and regenerates the signal.

Abstract translation: 目的：通过根据接收信号的自身时钟和时钟之间的相位差存储数据的转换信号，并比较从接收信号获得的存储内容和数据转换，消除对模拟组件的需要。 构成：触发器20-25移动信号并将其一次存储在触发器28中并响应于分频器29的输出时钟（f）写入ROM26中。ROM26参考预先书写的表 具有输入数据并生成输出数据。 触发器27在一个时钟之前锁存输出数据Qn和输出数据Qn-1，响应于分频器29的时钟将数据Qn输出到光学LSI链路发送器30，并反馈数据Qn-1 ，Qn和针对ROM26的数据Qn-1，Qn提供的相位差的数据。 ROM26鉴别出数据中的位错误并再生信号。

公开(公告)号：JPS58195342A

公开(公告)日：1983-11-14

申请号：JP7857882

申请日：1982-05-11

Applicant: Fujitsu Ltd

Inventor： NAKAHARA YASUHIRO ,  MITA TERUYOSHI

IPC: G06F13/00 ,  H04L12/52

CPC classification number: H04L12/525

Abstract: PURPOSE:To attain ease change in system constitution and to make economical constitution possible, by providing a frame counter and a channel control table to a common control section and discriminating whether or not a line corresponding section of itself is selected based on the information. CONSTITUTION:A transmission line controlling section 13 of the common control section 4 adds the frame counter FC 14 by +1 when one time slot TS is received. The counted value is an address of a channel controlling table 16. When the content of an area of a control table 16 corresponding to the received TS is other than an underfined number, the content and the data of the received TS are transmitted to each circuit corresponding section 5 in common. When the content is the underfined number, the common control section 4 waits for the reception of the next TS. The line corresponding section 5 performs a comparison and collation between the notified corresponding number and the corresponding number of a TS controlling area 12 in the line corresponding section of itself at a TS comparison section 15. When both are coincident, the line corresponding section 5 transmits the data of the said TS to a terminal 10 or a data processor 11.

Abstract translation: 目的：通过向公共控制部提供帧计数器和信道控制表，并且基于该信息来区分是否选择了自身的线路对应部分，为了实现系统结构的轻松改变并且使得经济的结构成为可能。 构成：当接收到一个时隙TS时，公共控制部分4的传输线控制部分13将帧计数器FC 14加1。 计数值是信道控制表16的地址。当与接收到的TS相对应的控制表16的区域的内容不是低估号码时，接收的TS的内容和数据被发送到每个电路 相应的第5节。 当内容是精细数量时，公共控制部分4等待下一个TS的接收。 线对应部分5在通过TS比较部分15自己的行对应部分中通知的对应号码和TS控制区域12的对应号码之间进行比较和核对。当两者一致时，行对应部分5发送 所述TS的数据到终端10或数据处理器11。