公开(公告)号：US20220122963A1

公开(公告)日：2022-04-21

申请号：US17072649

申请日：2020-10-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8258

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US11282740B2

公开(公告)日：2022-03-22

申请号：US16992165

申请日：2020-08-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy

IPC: H01L21/00 ,  H01L21/763 ,  H01L29/06 ,  H01L29/04

Abstract: Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module).

公开(公告)号：US11264457B1

公开(公告)日：2022-03-01

申请号：US16953897

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Siva P. Adusumilli ,  Steven M. Shank ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L21/763 ,  H01L27/06 ,  H01L21/762

Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.

公开(公告)号：US20210296122A1

公开(公告)日：2021-09-23

申请号：US16821228

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/762

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

公开(公告)号：US12002878B2

公开(公告)日：2024-06-04

申请号：US18085677

申请日：2022-12-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark Levy ,  Jeonghyun Hwang

IPC: H01L29/778 ,  H01L27/088 ,  H01L29/04 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L27/088 ,  H01L29/04 ,  H01L29/1602 ,  H01L29/2003 ,  H01L29/66462

Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

公开(公告)号：US11949034B2

公开(公告)日：2024-04-02

申请号：US17849285

申请日：2022-06-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Siva P. Adusumilli ,  Ramsey Hazbun

IPC: H01L31/105 ,  H01L31/0288 ,  H01L31/18 ,  H01L31/0216

CPC classification number: H01L31/105 ,  H01L31/0288 ,  H01L31/1804 ,  H01L31/0216

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodetector and methods of manufacture. The structure includes: a photodetector; and a semiconductor material on the photodetector, the semiconductor material comprising a first dopant type, a second dopant type and intrinsic semiconductor material separating the first dopant type from the second dopant type.

公开(公告)号：US20240014101A1

公开(公告)日：2024-01-11

申请号：US17858660

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Cameron Luce ,  Siva P. Adusumilli ,  Mark Levy

IPC: H01L23/473 ,  H01L23/367 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L23/473 ,  H01L23/367 ,  H01L21/76229 ,  H01L29/515

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

公开(公告)号：US20240009668A1

公开(公告)日：2024-01-11

申请号：US17858461

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Siva P. Adusumilli ,  Mark Levy ,  Bartlomiej Jan Pawlak

IPC: B01L3/00 ,  B81B1/00 ,  B81C1/00

CPC classification number: B01L3/50273 ,  B81B1/002 ,  B81C1/00071 ,  B81B2201/05 ,  B81B2203/0338 ,  B01L2300/0645 ,  B01L2300/12 ,  B01L2400/0424

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a semiconductor substrate including a trench and a layer stack on the semiconductor substrate. The layer stack includes a first layer, a second layer between the first layer and the semiconductor substrate, and an opening penetrating through the first layer and the second layer to the trench. The structure further comprises a third layer inside the opening in the layer stack. The third layer, which comprises a semiconductor material, obstructs the opening to define a cavity inside the trench.

公开(公告)号：US11768337B2

公开(公告)日：2023-09-26

申请号：US17362154

申请日：2021-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Spencer Porter ,  Mark Levy ,  Siva P. Adusumilli ,  Yusheng Bian

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/12

CPC classification number: G02B6/4203 ,  G02B6/1225 ,  G02B2006/12104 ,  G02B2006/12159

Abstract: Structures for a coupler and methods of forming a structure for a coupler. A structure for a directional coupler may include a first waveguide core having one or more first airgaps and a second waveguide core including one or more second airgaps. The one or more second airgaps are positioned in the second waveguide core adjacent to the one or more first airgaps in the first waveguide core. A structure for an edge coupler is also provided in which the waveguide core of the edge coupler includes one or more airgaps.

公开(公告)号：US20230223337A1

公开(公告)日：2023-07-13

申请号：US17572681

申请日：2022-01-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Fuad H. Al-Amoody ,  Siva P. Adusumilli ,  Spencer H. Porter ,  Ephrem Gebreselasie ,  Rajendran Krishnasamy

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/36 ,  H01L23/34 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76877 ,  H01L23/36 ,  H01L23/345 ,  H01L21/76832 ,  H01L23/5226 ,  H01L21/76816

Abstract: A semiconductor structure includes a semiconductor device (e.g., an e-fuse or photonic device) and a metallic heating element adjacent thereto. The heating element has a lower portion within a middle of the line (MOL) dielectric layer adjacent to the semiconductor device and an upper portion with a tapered top end that extends into a back end of the line (BEOL) dielectric layer. A method of forming the semiconductor structure includes forming a cavity such that it has both a lower section, which extends from a top surface of a MOL dielectric layer downward toward a semiconductor device, and an upper section, which extends from the top surface of the MOL dielectric layer upward and which is capped by an area of a BEOL dielectric layer having a concave bottom surface. A metallic fill material can then be deposited into the cavity (e.g., through via openings) to form the heating element.