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    91.
    发明专利
    未知

    公开(公告)号：AT358331T

    公开(公告)日：2007-04-15

    申请号：AT95929600

    申请日：1995-08-17

    Applicant: INT RECTIFIER CORP

    Inventor： KINZER DANIEL M

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/332 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78

    Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

    95.
    发明专利
    未知

    公开(公告)号：ITMI972545A1

    公开(公告)日：1999-05-17

    申请号：ITMI972545

    申请日：1997-11-17

    Applicant: INT RECTIFIER CORP

    Inventor： KINZER DANIEL M

    IPC: H01L21/302 ,  H01L21/223 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78

    Abstract: An MOS-gated power semiconductor device is formed by a process that uses a reduced number of masking steps and minimizes the number of critical alignments. A first photolithographic masking step defines the body or channel region and the source region of each of the cells. A second photolithographic step is aligned to a small central area above the source region of each of the cells or strips, the only critical alignment in the process, and is used to define openings in a protective oxide layer which, in turn, masks the etching of depressions in the substrate surface and the formation of a contact region. An isotropic etch undercuts the protective oxide to expose shoulders at the silicon surface of the chip which surround the etched holes. A conductive layer fills the holes and thus contacts the underlying body regions and overlaps the shoulders surrounding the source regions at the silicon surface. The conductive layer is sintered at a temperature that is sufficiently high to achieve low contact resistance between the metal and body regions but is low enough to be tolerated by the conductive layer.

    MOS-gated semiconductor device
    97.
    发明专利
    MOS-gated semiconductor device 未知

    公开(公告)号：GB2319395A

    公开(公告)日：1998-05-20

    申请号：GB9724413

    申请日：1997-11-18

    Applicant: INT RECTIFIER CORP

    Inventor： KINZER DANIEL M

    IPC: H01L21/302 ,  H01L21/223 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L21/328 ,  H01L29/70

    Abstract: An MOS-gated power semiconductor device such as an IGBT or MOS-gated thyristor is formed by a process that uses a reduced number of masking steps and minimizes the number of critical alignments. A first photolithographic masking step defines the body 30 or channel region and the source region 50,51 of each of the cells. A second photolithographic step is aligned to a small central area above the source region of each of the cells or strips, the only critical alignment in the process, and is used to define openings in a protective oxide layer 61 which, in turn, masks the etching of depressions in the substrate surface and the formation of a contact region. An isotropic etch undercuts the protective oxide to expose shoulders at the silicon surface of the chip which surround the etched holes. A conductive layer 84 fills the holes and thus contacts the underlying body regions and overlaps the shoulders surroundings the source regions at the silicon surface. The conductive layer is sintered at a temperature that is sufficiently high to achieve low contact resistance between the metal and body regions but is low enough to be tolerated by the conductive layer.

    MOS gated device with self aligned cells
    98.
    发明专利
    MOS gated device with self aligned cells 未知

    公开(公告)号：GB2318685A

    公开(公告)日：1998-04-29

    申请号：GB9722653

    申请日：1997-10-24

    Applicant: INT RECTIFIER CORP

    Inventor： KINZER DANIEL M

    IPC: H01L21/28 ,  H01L21/332 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/08

    Abstract: An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed, without any critical alignments thereby allowing the cell density to be increased. A sidewall spacer 62 is used to mask the etching of a depression in the silicon to reduce the number of critical mask alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.

    100.
    发明专利
    未知

    公开(公告)号：FR2739976A1

    公开(公告)日：1997-04-18

    申请号：FR9612435

    申请日：1996-10-11

    Applicant: INT RECTIFIER CORP

    Inventor： KINZER DANIEL M ,  WAGERS KENNETH

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L21/334 ,  H01L21/328 ,  H01L29/68

    Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

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