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    Memory arrays with bonded and shared logic circuitry
    94.
    发明授权
    Memory arrays with bonded and shared logic circuitry 有权

    公开(公告)号：US10923450B2

    公开(公告)日：2021-02-16

    申请号：US16437445

    申请日：2019-06-11

    Applicant: Intel Corporation

    Inventor： Richard Fastow ,  Khaled Hasnat ,  Prashant Majhi ,  Owen W. Jungroth ,  Krishna Parat

    IPC: H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11573 ,  H01L25/18

    Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

    Deuterium-based passivation of non-planar transistor interfaces
    97.
    发明授权
    Deuterium-based passivation of non-planar transistor interfaces 有权

    公开(公告)号：US10692974B2

    公开(公告)日：2020-06-23

    申请号：US15753739

    申请日：2015-09-18

    Applicant: INTEL CORPORATION

    Inventor： Prashant Majhi ,  Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Aravind S. Killampalli ,  Mark R. Brazier ,  Jaya P. Gupta

    IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

    RRAM devices and their methods of fabrication
    98.
    发明授权
    RRAM devices and their methods of fabrication 有权

    公开(公告)号：US10658586B2

    公开(公告)日：2020-05-19

    申请号：US16099173

    申请日：2016-07-02

    Applicant: Intel Corporation

    Inventor： James S. Clarke ,  Ravi Pillarisetty ,  Uday Shah ,  Tejaswi K. Indukuri ,  Niloy Mukherjee ,  Elijah V. Karpov ,  Prashant Majhi

    IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

    Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.

    SELECTOR DEVICES WITH INTEGRATED BARRIER MATERIALS
    99.
    发明申请
    SELECTOR DEVICES WITH INTEGRATED BARRIER MATERIALS 审中-公开

    公开(公告)号：US20200075851A1

    公开(公告)日：2020-03-05

    申请号：US16114713

    申请日：2018-08-28

    Applicant: Intel Corporation

    Inventor： Elijah V. Karpov ,  Brian S. Doyle ,  Prashant Majhi ,  Abhishek A. Sharma ,  Ravi Pillarisetty

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Disclosed herein are selector devices and related devices and techniques. For example, in some embodiments, a selector device may include a first electrode, a second electrode, and a selector material stack between the first electrode and the second electrode. The selector material stack may include a dielectric material layer between a first conductive material layer and a second conductive material layer. A first material layer may be present between the first electrode and the first conductive material layer, and a second material layer may be present between the first conductive material layer and the dielectric layer. The first material layer and the second material layer may be diffusion barriers, and the second material layer may be a weaker diffusion barrier than the first material layer.

    Techniques for forming non-planar resistive memory cells
    100.
    发明授权
    Techniques for forming non-planar resistive memory cells 有权

    公开(公告)号：US10439134B2

    公开(公告)日：2019-10-08

    申请号：US15117594

    申请日：2014-03-25

    Applicant: INTEL CORPORATION

    Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Uday Shah ,  Niloy Mukherjee ,  Charles C. Kuo ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Robert S. Chau

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

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