公开(公告)号：US10803548B2

公开(公告)日：2020-10-13

申请号：US16355377

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20200294179A1

公开(公告)日：2020-09-17

申请号：US16355274

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Nicolas Galoppo von Borries ,  Varghese George ,  Altug Koker ,  Elmoustapha Ould-Ahmed-Vall ,  Mike Macpherson ,  Subramaniam Maiyuran

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/38 ,  G06T15/00

Abstract: Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

公开(公告)号：US20200293369A1

公开(公告)日：2020-09-17

申请号：US16355565

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Varghese George ,  Altug Koker ,  Aravindh Anantaraman ,  SungYe Kim ,  Valentin Andrei ,  Joydeep Ray

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/30 ,  G06F12/0837

Abstract: Accelerated synchronization operations using fine grain dependency check are disclosed. A graphics multiprocessor includes a plurality of execution units and synchronization circuitry that is configured to determine availability of at least one execution unit. The synchronization circuitry to perform a fine grain dependency check of availability of dependent data or operands in shared local memory or cache when at least one execution unit is available.

公开(公告)号：US10761898B2

公开(公告)日：2020-09-01

申请号：US15672086

申请日：2017-08-08

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Varghese George ,  Inder M. Sodhi

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/30

Abstract: Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

公开(公告)号：US20190179531A1

公开(公告)日：2019-06-13

申请号：US16274866

申请日：2019-02-13

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

IPC: G06F3/06 ,  G06F15/78 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/06 ,  G06F1/3287 ,  G11C5/04

Abstract: A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

公开(公告)号：US20170269672A9

公开(公告)日：2017-09-21

申请号：US14966708

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US09690353B2

公开(公告)日：2017-06-27

申请号：US13799524

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Douglas Moran ,  Achmed Rumi Zahir ,  William Knolla ,  Hartej Singh ,  Vasudev Vasu Bibikar ,  Sanjeev Jahagirdar ,  Michael Klinglesmith ,  Irwin Vaz ,  Varghese George

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

公开(公告)号：US20170147214A1

公开(公告)日：2017-05-25

申请号：US15427880

申请日：2017-02-08

Applicant: INTEL CORPORATION

Inventor： Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

IPC: G06F3/06 ,  G06F12/0811 ,  G06F15/78 ,  G06F1/32

CPC classification number: G06F3/061 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0811 ,  G06F15/781 ,  G06F2212/283 ,  G06F2212/7206 ,  G11C5/04

Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

公开(公告)号：US09626316B2

公开(公告)日：2017-04-18

申请号：US14141828

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Joydeep Ray ,  Varghese George

IPC: G06F13/36 ,  G06F9/52

CPC classification number: G06F13/36 ,  G06F9/52

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.

公开(公告)号：US20160140081A1

公开(公告)日：2016-05-19

申请号：US15007450

申请日：2016-01-27

Applicant: Intel Corporation

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev S. Jahagirdar ,  Oren Lamdan

IPC: G06F15/82 ,  G06F9/30

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.