公开(公告)号：US11221762B2

公开(公告)日：2022-01-11

申请号：US16274866

申请日：2019-02-13

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C5/04 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/78

Abstract: A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

公开(公告)号：US20160041595A1

公开(公告)日：2016-02-11

申请号：US14919780

申请日：2015-10-22

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Jeffrey R. Wilcox ,  Michael N. Derr ,  Neil W. Songer ,  Craig S. Forbell

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

公开(公告)号：US20170212832A1

公开(公告)日：2017-07-27

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/42 ,  G06F13/12 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US09794349B2

公开(公告)日：2017-10-17

申请号：US14554513

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Naveen Cherukuri ,  Aaron T. Spink ,  Phanindra Mannava ,  Tim Frodsham ,  Jeffrey R. Wilcox ,  Sanjay Dabral ,  David Dunning ,  Theodore Z. Schoenborn

IPC: H04L29/08 ,  G06F13/42 ,  H04L29/06

CPC classification number: H04L67/141 ,  G06F13/4265 ,  H04L65/60 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

公开(公告)号：US20190179531A1

公开(公告)日：2019-06-13

申请号：US16274866

申请日：2019-02-13

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

IPC: G06F3/06 ,  G06F15/78 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/06 ,  G06F1/3287 ,  G11C5/04

Abstract: A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

公开(公告)号：US09910771B2

公开(公告)日：2018-03-06

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US20170147214A1

公开(公告)日：2017-05-25

申请号：US15427880

申请日：2017-02-08

Applicant: INTEL CORPORATION

Inventor： Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

IPC: G06F3/06 ,  G06F12/0811 ,  G06F15/78 ,  G06F1/32

CPC classification number: G06F3/061 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0811 ,  G06F15/781 ,  G06F2212/283 ,  G06F2212/7206 ,  G11C5/04

Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

公开(公告)号：US09535829B2

公开(公告)日：2017-01-03

申请号：US14128669

申请日：2013-07-26

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract translation: 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

公开(公告)号：US20150081921A1

公开(公告)日：2015-03-19

申请号：US14554513

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Naveen Cherukuri ,  Aaron T. Spink ,  Phanindra Mannava ,  Tim Frodsham ,  Jeffrey R. Wilcox ,  Sanjay Dabral ,  David Dunning ,  Theodore Z. Schoenborn

IPC: H04L29/08 ,  H04L29/06

CPC classification number: H04L67/141 ,  G06F13/4265 ,  H04L65/60 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Abstract translation: 管理链路的系统和方法提供了在链路初始化期间接收远程宽度能力，即对应于远程端口的远程宽度能力。 根据远程宽度能力，本地端口和远程端口之间的链路以多个链路宽度进行操作。

公开(公告)号：US10228861B2

公开(公告)日：2019-03-12

申请号：US15427880

申请日：2017-02-08

Applicant: INTEL CORPORATION

Inventor： Joydeep Ray ,  Varghese George ,  Inder M. Sodhi ,  Jeffrey R. Wilcox

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C5/04 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/78

Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.