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    TECHNOLOGIES FOR FABRIC SUPPORTED SEQUENCERS IN DISTRIBUTED ARCHITECTURES
    91.
    发明申请
    TECHNOLOGIES FOR FABRIC SUPPORTED SEQUENCERS IN DISTRIBUTED ARCHITECTURES 审中-公开

    公开(公告)号：US20180077270A1

    公开(公告)日：2018-03-15

    申请号：US15260613

    申请日：2016-09-09

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

    IPC: H04L29/08 ,  H04L12/50 ,  H04L1/16

    CPC classification number: H04L69/324 ,  G06F15/173 ,  H04L1/1642 ,  H04L12/50 ,  H04L49/00

    Abstract: Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.

    DATA ACCESS BETWEEN COMPUTING NODES
    93.
    发明申请
    DATA ACCESS BETWEEN COMPUTING NODES 审中-公开

    公开(公告)号：US20170344283A1

    公开(公告)日：2017-11-30

    申请号：US15167953

    申请日：2016-05-27

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Alejandro Duran Gonzalez ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0284 ,  G06F2212/2542

    Abstract: Technology for an apparatus is described. The apparatus can receive a command to copy data. The command can indicate a first address, a second address and an offset value. The apparatus can determine a first non-uniform memory access (NUMA) domain ID for the first address and a second NUMA domain ID for the second address. The apparatus can identify a first computing node with memory that corresponds to the first NUMA domain ID and a second computing node with memory that corresponds to the second NUMA domain ID. The apparatus can generate an instruction for copying data in a first memory range of the first computing node to a second memory range of the second computing node. The first memory range can be defined by the first address and the offset value and the second memory range can be defined by the second address and the offset value.

    Hardware-assisted tracing schemes for distributed and scale-out applications
    96.
    发明授权
    Hardware-assisted tracing schemes for distributed and scale-out applications 有权

    公开(公告)号：US12231487B2

    公开(公告)日：2025-02-18

    申请号：US16790342

    申请日：2020-02-13

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Patrick Kutch ,  Trevor Cooper ,  Timothy Verrall ,  Karthik Kumar

    IPC: H04L67/10 ,  H04L41/14

    Abstract: Methods and apparatus for scale out hardware-assisted tracing schemes for distributed and scale-out applications. In connection with execution of one or more applications using a distributed processing environment including multiple compute nodes, telemetry and tracing data are obtained using hardware-based logic on the compute nodes. Processes associated with applications are identified, as well as the compute nodes on which instances of the processes are executed. Process instances are associated with process application space identifiers (PASIDs), while processes used for an application are associating with a global group identifier (GGID) that serves as an application ID. The PASIDs and GGIDs are used to store telemetry and/or tracing data on the compute nodes and/or forward such data to a tracing server in a manner that enables telemetry and/or tracing data to be aggregated on an application basis. Telemetry and/or tracing data may be obtained from processors on the compute nodes, and (optionally) additional elements such as network interface controllers (NICs). Tracing data may also be obtained from switches used for forwarding data between processes.

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