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公开(公告)号：US20210273650A1
公开(公告)日：2021-09-02
申请号：US16807065
申请日：2020-03-02
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
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公开(公告)号：US20250165403A1
公开(公告)日：2025-05-22
申请号：US19024060
申请日：2025-01-16
Applicant: Micron Technology, Inc.
Inventor： Sanjay Subbarao , James Fitzpatrick
IPC: G06F12/0882 , G06F12/02 , G06F12/0811 , G11C11/56
Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.
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公开(公告)号：US20250103230A1
公开(公告)日：2025-03-27
申请号：US18781692
申请日：2024-07-23
Applicant: Micron Technology, Inc.
Inventor： Dung Viet Nguyen , Phong S. Nguyen , James Fitzpatrick
IPC: G06F3/06
Abstract: Host data to be programmed to a plurality of memory cells associated with a wordline of a memory device is received from a host system. The host data into a plurality of partitions is divided. Each of the plurality of partitions is divided into a respective plurality of sub-partitions. One or more modulation mappings to be applied to the plurality of sub-partitions are determined based on the host data of the plurality of partitions. Host data of each sub-partition of the plurality of sub-partitions is modified based on the one or more modulation mappings. The modified host data of each sub-partition is written to the plurality of memory cells associated with the wordline.
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公开(公告)号：US12217803B2
公开(公告)日：2025-02-04
申请号：US17742345
申请日：2022-05-11
Applicant: Micron Technology, Inc.
Inventor： Abdelhakim S. Alhussien , James Fitzpatrick , Patrick Robert Khayat , Sivagnanam Parthasarathy
Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.
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公开(公告)号：US12131060B2
公开(公告)日：2024-10-29
申请号：US17872426
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0679
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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Patent Agency Ranking
公开(公告)号：US12105961B2
公开(公告)日：2024-10-01
申请号：US17978890
申请日：2022-11-01
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Patrick R. Khayat , Sead Zildzic , Violante Moschiano , James Fitzpatrick
CPC classification number: G06F3/0611 , G06F3/064 , G06F3/0679 , G11C16/3459 , G11C29/52
Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.
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公开(公告)号：US12073891B2
公开(公告)日：2024-08-27
申请号：US17682089
申请日：2022-02-28
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Violante Moschiano , Jeffrey S. McNeil , James Fitzpatrick , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Patrick R. Khayat
CPC classification number: G11C16/30 , G11C16/102 , G11C16/26 , G11C2207/2254
Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.
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98.发明公开公开(公告)号：US20240265979A1
公开(公告)日：2024-08-08
申请号：US18636901
申请日：2024-04-16
Applicant: Micron Technology, Inc.
Inventor： James Fitzpatrick , Phong Sy Nguyen , Dung Viet Nguyen , Sivagnanam Parthasarathy
CPC classification number: G11C16/3404 , A63B24/0075 , G11C16/26 , A63B2024/0068 , A63B2024/0093 , A63B2220/836 , A63B2230/06
Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
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公开(公告)号：US20240232013A1
公开(公告)日：2024-07-11
申请号：US18611450
申请日：2024-03-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Niccolo’ Righetti , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Mark A. Helm , James Fitzpatrick , Ugo Russo
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/1435
Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.
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公开(公告)号：US12009034B2
公开(公告)日：2024-06-11
申请号：US16807065
申请日：2020-03-02
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat , Abdelhakim S. Alhussien
CPC classification number: G11C16/26 , G06F9/30021 , G06F9/30101 , G06F9/3804 , G06F18/24323 , H03M13/015 , H03M13/612
Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
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