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公开(公告)号：JPH10307708A
公开(公告)日：1998-11-17
申请号：JP11471697
申请日：1997-05-02
Applicant: SONY CORP
Inventor： OZAKI YASUNARI , IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To generate the orthogonal function of the range of 0-2π from the data of the range of 0-π/4. SOLUTION: The data for which high order 3 bits are excluded from address data corresponding to a phase angle are supplied to a selector 21 and supplied to a subtraction circuit 20 and subtracted from an address value (Adr Max) corresponding to π/4. The selector 21 selects and outputs the data for which the high order 3 bits are excluded in the case that a third bit is '0' and selects and outputs the output of the subtraction circuit 20 in the case that the third bit is '1'. A ROM 24 stores the data of the range of 0-π/4 and supplies the data corresponding to the output of the selector 21 to the selector 25. The selector 25 selects the output from a constant value supply circuit 26 in the case that a judgement circuit 22 judges that an address for which the high order 3 bits are excluded is '0' and selects and outputs the output from the ROM 24 in the other case. For the output data of the selector 25, a code is appropriately inverted by code inversion circuits 27 and 28, a real number part and an imaginary number part are appropriately replaced by the selectors 29-34 and they are outputted.
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公开(公告)号：JPH10262224A
公开(公告)日：1998-09-29
申请号：JP6566197
申请日：1997-03-19
Applicant: JISEDAI DIGITAL TELE HOSO SYS , SONY CORP
Inventor： IKEDA YASUNARI , SHIROTA NORIHISA
Abstract: PROBLEM TO BE SOLVED: To provide a digital broadcast/communication system in which convenience for connecting a studio with a report site is improved. SOLUTION: A forward error correction(FEC) circuit 11 applies error correction coding to a broadcast information series, an IL circuit 12 applies interleaving to the resulting data, a MAP circuit 13 assigns the result to a signal point of a broadcast channel, on the other hand, a FEC circuit 21 conducts stronger error correction coding than that of the FEC circuit 11 to a communication information series, a MAP circuit 23 assigns the result to a signal point of a communication channel, a MUX circuit 30 multiplexes an output information series of the MAP circuit 13, 23 and an OFDM modulator 40 modulates an OFDM to obtain a secondary modulation signal. This signal is transmitted as a broadcast wave. A receiver side extracts and demodulates the communication information series from the broadcast wave, then a report site receives instruction information or the like that is transmitted on the broadcast wave from a studio.
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公开(公告)号：JPH1049516A
公开(公告)日：1998-02-20
申请号：JP20154696
申请日：1996-07-31
Applicant: SONY CORP
Inventor： ITO YASU , OZAKI YASUNARI , IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To improve the using efficiency of a memory and to reduce the cost of an arithmetic unit. SOLUTION: In the case of executing a butterfly operation of 11 steps for 2048 data, bit shifting processing is executed for all operation results of 5-th, 7th and 10th butterfly operation to compress the dynamic range of data. Thus the butterfly operation of 11 steps is executed by utilizing a memory of 10 bits for each input data consisting of 8 bits.
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公开(公告)号：JPH09247122A
公开(公告)日：1997-09-19
申请号：JP5437496
申请日：1996-03-12
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , MIYATO YOSHIKAZU
Abstract: PROBLEM TO BE SOLVED: To correctly and easily generate a window synchronization signal in a DAB system receiver. SOLUTION: A tuner 2 extracts a desired signal from an RF signal which is received by an antenna 1 and an IF circuit 3 extracts I data and Q data. I data and Q data are supplied to a null signal detecting circuit 71, the null signal is detected and a time base circuit 7b generates a timing signal for generating a window by synchronizing with the timing of the detected null signal. A window generating circuit 7c synchronizes with the timing signal which is supplied from the time base circuit 7b so as to generate the window synchronization signal.
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公开(公告)号：JP2586299B2
公开(公告)日：1997-02-26
申请号：JP19368493
申请日：1993-08-04
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , MORITA HIDEO , KURATA YUKINOBU
IPC: H04N19/50 , H04N7/14 , H04N19/423 , H04N19/593 , H04N19/70 , H04N19/85 , H04N21/4402 , H04N7/32
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Patent Agency Ranking
公开(公告)号：JP2545845B2
公开(公告)日：1996-10-23
申请号：JP8031787
申请日：1987-03-31
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , MORITA HIDEO , KURATA YUKINOBU
IPC: H04N9/65
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公开(公告)号：JPH06205412A
公开(公告)日：1994-07-22
申请号：JP17261993
申请日：1993-06-18
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , HATAKE SHOHEI , YASUI HIROYUKI
Abstract: PURPOSE:To prevent a display picture from being disturbed due to distrubance in synchronization by providing a means for muting a display device corresponding to a synchronization state and its instruction to a part of a transmission line. CONSTITUTION:A reception side is provided with a split separating section 31, signal switching sections 32, 33 for switching a reception signal or the output of the split separating section 31 with the instruction and plural display devices 40, 41 and a signal from a transmission side is transmitted to the reception side via a line 13. A means for muting the display devices 40, 41 is provided on a part of the transmission line corresponding to the synchronization state and the instruction. When a split synthesis screen or a screen not split synthesis is selected at the transmission side, or a pattern subjected to split separation or a pattern not subjected to split separation is selected at a reception side, till the vertical synchronization is taken and the operation is made stable, a video signal level is set to a black level and muting is applied. Thus, the appearance of disturbance of synchronization on the pattern is prevented.
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公开(公告)号：JPH05300488A
公开(公告)日：1993-11-12
申请号：JP10484992
申请日：1992-04-23
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , SETO HIROAKI
Abstract: PURPOSE:To realize a circuit operating by a single clock and having the access speed of a RAM which is half as much as a conventional one. CONSTITUTION:Four RAMs having the capacity where the data for n lines is possible to be written are prepared. 1, 2, 3, 4 are RAMs, 11, 12, 13, 14 and 21, 22, 23, 24 are switches, and 31, 32 are selectors. Maximum three of the 4 RAMs in this circuit become reading modes and the remaining one becomes a writing mode. Namely, as one RAM operates as if it is exclusive for writing, the operating of the RAM by the clock with twice frequency like a conventional way is unnecessitated. In this circuit, a RAM always operates exclusively for writing. In accordance with the lowering of the range of processings, the RAM exclusive for writing is replaced in turn.
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公开(公告)号：JPH05291831A
公开(公告)日：1993-11-05
申请号：JP8563592
申请日：1992-04-07
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , TAMURA YOSHIHIRO
Abstract: PURPOSE:To extend a break point frequency of a frequency characteristic toward a lower limit by detecting a DC component of an output of a drive amplifier and comparing it with a reference value so as to apply DC feedback to the drive amplifier. CONSTITUTION:The circuit is provided with a drive amplifier 5 receiving a modulation signal, a modulator 1 receiving the output of the drive amplifier 5, a comparator 7 detecting a DC component based on outputs of the drive amplifier 5 and of the modulator 1 receiving the output of the drive amplifier 5 and comparing the component with a reference value to obtain a comparison use DC current. Then a DC component in a modulation signal V1 detected by a low pass filter (LPF) 6 is subtracted from a reference voltage corresponding to an offset of the modulator 1 at the comparator 7 and a difference DC component is fed back to the drive amplifier 5, in which the offset component caused in advance in the modulator 1 is similarly subtracted and a modulation signal is fed to the modulator 1. Thus, the low frequency component included in the modulation signal V1 is not attenuated nor eliminated.
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公开(公告)号：JPH03201892A
公开(公告)日：1991-09-03
申请号：JP34427189
申请日：1989-12-28
Applicant: TOKYO ELECTRIC POWER CO , SONY CORP
Inventor： HATTORI SEIJI , KIMURA HIROSHIGE , SHIMIZU HIDEO , IKEDA YASUNARI , SAWARA HIROSHI
Abstract: PURPOSE:To prevent deterioration in picture quality due to blooming by detecting a current flowing to a flyback transformer of a monitor and controlling a level of a video signal outputted from a storage element based on the result of detection. CONSTITUTION:A current flowing to a flyback transformer 21 of a monitor 20 is detected and when the detected current is less, a level of a video signal outputted from a storage element 9 is decreased and when the detected current is much conversely, the level of the video signal outputted from the storage element 9 is increased. Thus, when the background is bright, the superimposing part is made bright to make the pattern to be observed easily and when the background is dark, the superimposed part is darker. Moreover, the level of the video signal outputted from the storage element 9 in the blackboard mode in which an average brightness level is low by decreasing the level of the video signal outputted from the storage element 9 in the superimposed mode and the blackboard mode.
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