公开(公告)号：JPS52103961A

公开(公告)日：1977-08-31

申请号：JP2040276

申请日：1976-02-26

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  MOCHIZUKI HIDENOBU ,  OOTSU KOUJI ,  AZUMA YOSHINORI

IPC: H01L29/78 ,  H01L21/31 ,  H01L21/336 ,  H01L29/94

Abstract: PURPOSE:To lower the threshold voltage of the FET which is in MNOS structure, by annealing the base board, which contains Si3N4 film, in the atmosphere which is mainly composed of H2 under the temperature of 900-950 deg.C.

公开(公告)号：JPS52101984A

公开(公告)日：1977-08-26

申请号：JP1872676

申请日：1976-02-23

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  INOUE KENICHI ,  YAMAGUCHI JIROU ,  MOCHIZUKI HIDENOBU ,  OOTSU KOUJI

IPC: H01L21/822 ,  H01L21/22 ,  H01L21/265 ,  H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L27/04 ,  H01L27/08 ,  H01L29/78

Abstract: PURPOSE:To prepare MOSIC of high integration by employing an ion injection method, and by piercing an aperture of source, drain and separation region with one time mask self matching of common mask.

公开(公告)号：JPS5291383A

公开(公告)日：1977-08-01

申请号：JP732076

申请日：1976-01-26

Applicant: SONY CORP

Inventor： MOCHIZUKI HIDENOBU ,  SHIMADA TAKASHI ,  MIFUNE TADAYOSHI

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To reduce the width of voltage and signal for write-in and the leakage of write-in electric charge, by increasing the number of traps at the Al2O3 layer and SiO2 layer, thru making the gate section of the memory transistor as the gate electrode, Si3N4 layer, Al2O3 layer, SiO2 layer and MNAOS configuration of the semiconductor base.

公开(公告)号：JPS51114069A

公开(公告)日：1976-10-07

申请号：JP3888175

申请日：1975-03-31

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  KASHIWANUMA AKIO

IPC: H01L29/73 ,  H01L21/28 ,  H01L21/283 ,  H01L21/30 ,  H01L21/331 ,  H01L29/10 ,  H01L29/74 ,  H01L29/744

Abstract: PURPOSE:Forming a depleticon layer under electrode by having the fourth semiconductor region corresponding to conductor 2 occur under the electrode extending over the first semiconductor region, and thereby achieving an effective countermeasure against insulation disruption.

公开(公告)号：JP2003021798A

公开(公告)日：2003-01-24

申请号：JP2001206452

申请日：2001-07-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： IKEDA KOICHI ,  SHIMADA TAKASHI

IPC: B81B7/02 ,  G02B26/08 ,  H01S3/10

CPC classification number: G02B26/0841 ,  G02B26/0808

Abstract: PROBLEM TO BE SOLVED: To provide an MEMS element having a membrane of such a constitution that it is not damaged in etching to remove a sacrificial layer when silicon, such as polysilicon and amorphous silicon, is used as the sacrificial layer. SOLUTION: This MEMS element 30 is constituted as an optical modulation element constituting a GVL device and has the same constitution as the constitution of the conventional MEMS element except that the structure of a bridge member 34 of the membrane 32 is different. The membrane 32 comprises the bridge member 34 which has an SiO2 film 36 of 20 nm in film thickness as a lower layer and is laminated with an SiN film 38 of, for example, 100 nm in film thickness thereon and a membrane side electrode 14 commonly used as a light reflection surface consisting of an Al film of 100 nm in film thickness formed on the bridge member 34. The SiO2 film 36 may be an SiO2 film formed by thermally oxidizing the sacrificial layer consisting of the polysilicon or an SiO2 film deposited by a CVD process or PVD process.

Abstract translation: 要解决的问题：提供一种MEMS元件，其具有这样的结构，即当诸如多晶硅和非晶硅之类的硅被用作牺牲层时，在蚀刻中不会损坏去除牺牲层。 解决方案：除了膜32的桥接构件34的结构不同之外，该MEMS元件30构成为构成GVL器件的光学调制元件，并且具有与常规MEMS元件的结构相同的结构。 膜32包括桥接构件34，其具有作为下层的膜厚度为20nm的SiO 2膜36，并且其膜厚膜例如为100nm的SiN膜38和通常的膜侧电极14层叠 用作由桥状构件34上形成的膜厚度为100nm的Al膜构成的光反射面.SiO 2膜36可以是通过热氧化由多晶硅构成的牺牲层或由 CVD工艺或PVD工艺。

公开(公告)号：JPH08139286A

公开(公告)日：1996-05-31

申请号：JP30296894

申请日：1994-11-11

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: G11C11/22 ,  G11C16/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To lower writing and erasing voltages without reducing an operating allowance and to easily read by reading the variation of a reading current. CONSTITUTION: A memory transistor 54 is transited between an enhancement state and a depletion state, and a reading transistor 44 is set to an enhancement type. Thus, the absolute values of the threshold voltages of the writing and erasing states can be reduced without decreasing the difference between the threshold voltages of the writing and erasing states. When the transistor 54 becomes the depletion state, the channel length of the transistor 44 is decided in a self-alignment manner according to the gate length.

公开(公告)号：JPH08139212A

公开(公告)日：1996-05-31

申请号：JP30296694

申请日：1994-11-11

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/8247 ,  H01L21/76 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To prevent increase of diffused layer resistance and parasitic junction capacitance by eliminating variation of width in the diffused layer resulting from positioning error. CONSTITUTION: After the diffused layers 16, 17 are formed by ion implantation from an aperture 12a of a Si3 N4 /SiO2 film 12, a part of the Si3 N4 /SiO2 film 12 is removed and a channel stop 14 is formed by the ion implantation utilizing this Si3 N4 /SiO2 film 12 as a mask. Therefore, any one of the boundary between the region where the diffused layers 16, 17 are not formed and the diffused layers 16, 17 and the boundary between the channel stop 14 and diffused layers 16, 17 is determined by the initial pattern of the Si3 N4 /SiO2 film 12.

公开(公告)号：JPH07245350A

公开(公告)日：1995-09-19

申请号：JP6002194

申请日：1994-03-04

Applicant: SONY CORP

Inventor： YAMAGISHI MACHIO ,  SHIMADA TAKASHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To improve storage performance of electric charge by excluding electric field concentration on the gate end of a two-layer gate structure like a nonvolatile storage device. CONSTITUTION:On the peripheral side of an element forming region 12 formed in a semiconductor substrate 11, an element isolation region 13 is formed in the upper layer. The height of the element isolation region 13 surface is made nearly equal to the height of the semiconductor substrate 11 surface. A first gate insulating film 14 and a first gate electrode 15 are laminated and formed in a part on the element forming region 12. In the gate width direction side of at least the first gate electrode 15, a flattened insulating film 16 is formed which has an upper surface having a height nearly equal to the height of the upper surface 15a of the first electrode 15. A second gate insulating film 17 and a second gate electrode 18 are laminated and formed on the upper surface 15a of the first gate electrode 15. The first gate electrode 15 is made a floating gate, and the second gate electrode is made a control gate. Hence a nonvolatile storage device is constituted.

公开(公告)号：JPH07147338A

公开(公告)日：1995-06-06

申请号：JP31909093

申请日：1993-11-24

Applicant: SONY CORP

Inventor： YAMAGISHI MACHIO ,  SHIMADA TAKASHI

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To enhance the holding capability of data by a method wherein a capacity between a first gate electrode and a second gate electrode for a semiconductor device whose gate is formed as a two-layer structure is ensured, a write voltage is restrained from increasing voltage and the concentration of an electric field in the first gate electrode is eliminated. CONSTITUTION:An element isolation region 13 is formed at the side circumference of an element formation region 12 in a semiconductor substrate 11, and a stepped part 14 is formed at the upper part or a part on the side of the element formation region 12 of the element isolation region 13. In addition, a first gate insulating film 15 is formed on the surface layer of the element formation region 12 in the semiconductor substrate 11, and a first gate electrode 16 is formed on the first gate insulating film 15 in a consecution state. Then, the surface 13a of the element isolation region 13 and the surface 16a of the first gate electrode 16 are formed nearly on the same plane. In addition, a second gate insulating film 17 and a second gate electrode 18 are laminated on the surface of the first gate electrode 16.

公开(公告)号：JPH0653100A

公开(公告)日：1994-02-25

申请号：JP20255992

申请日：1992-07-29

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: G01B11/24 ,  G01B17/00 ,  H01L21/02 ,  H01L21/66 ,  H01L21/68

Abstract: PURPOSE:To eliminate an invalid area due to the orientation flat of a semiconductor wafer for effective utilization. CONSTITUTION:A minute plane-shaped mark 13 indicating the crystal orientation of a wafer 11 is formed at one part of a round beveling part of the disk-shaped- wafer 11 consisting of a periphery end face part 14 constituted by the round beveling part, an optical detector 20 consisting of a photo coupler 21 is laid out on a normal line passing through the center of the wafer 11 on the extension line on the plane of the wafer 11, a light is applied to the periphery end face 14 of the wafer 11, the light reflected from the mark 13 is detected, and then the crystal orientation of the wafer 11 is detected, thus utilizing the surface area of a wafer fully, applying a crystal orientation mark, and hence improving a logic yield and a yield.