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公开(公告)号：JPH02210989A
公开(公告)日：1990-08-22
申请号：JP26578488
申请日：1988-10-21
Applicant: SONY CORP
Inventor： NAITO HIDEFUMI , SARUGAKU TOSHIO , TOKUHARA MASAHARU
Abstract: PURPOSE:To reduce flicker on the screen when a reproduced signal from a VTR is watched by shifting a vertical synchronizing pulse in the time base direction so as to appear earlier than a vertical synchronizing signal by a prescribed horizontal period. CONSTITUTION:The television receiver consists of a counter 19, latch circuits 21, 23, comparators 24, 27, a sub counter 26, an AND circuit 25 as a vertical synchronizing pulse forming means and of a sub counter 20 as a control means. A vertical synchronizing pulse forming means uses a vertical synchronizing signal VS of the standard TV signal from a terminal 18 and a clock signal from a terminal 22 to form a vertical synchronizing pulse 28a having frequency twice the frequency of the signal VS whose field frequency is doubled. In this case, the control means shifts the pulse 28a in the time base direction so that the pulse appears earlier than the signal VS by a prescribed horizontal period. Since distortion due to a skew signal is included in an over scan region and does not appears on the effective picture screen, the video signal due to the skew signal is not distorted.
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公开(公告)号：JPH02143777A
公开(公告)日：1990-06-01
申请号：JP29784988
申请日：1988-11-25
Applicant: SONY CORP
Inventor： NAITO HIDEFUMI , SARUGAKU TOSHIO , TOKUHARA MASAHARU
Abstract: PURPOSE:To prevent production of vertical jitter due to a clock signal when a vertical synchronizing signal pulse is formed from a vertical synchronizing signal separated from a video signal by using 1st and 2nd latch pulses so as to latch a vertical synchronizing signal at a specific time. CONSTITUTION:When an initial point of a vertical synchronizing signal enters a window period of a 1st window signal 18a, a 2nd latch pulse 19b is used to latch a vertical synchronizing signal Vs and when the first point of the vertical synchronizing signal Vs enters a window period of a 2nd window signal 18b, a 1st latch pulse 19a is used to latch the vertical synchronizing signal Vs to obtain a vertical synchronizing pulse. Thus, the production of vertical jitter by a clock signal is not caused when the vertical synchronizing pulse is generated from the vertical synchronizing signal is separated from the video signal.
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公开(公告)号：JPH0289477A
公开(公告)日：1990-03-29
申请号：JP24136588
申请日：1988-09-27
Applicant: SONY CORP
Inventor： NAITO HIDEFUMI , SARUGAKU TOSHIO , TOKUHARA MASAHARU
Abstract: PURPOSE:To reduce flicker of a VTR picture without deteriorating the quality of a picture even if number of horizontal scanning lines is fluctuated by writing a video signal in a storage means with a larger capacity than that of an effective pattern while inhibiting the write as required and reading out the signal at a double speed at that of the write while similarly inhibiting readout as required similarly. CONSTITUTION:The length of a write control signal from a flicker reduction circuit 29 is detected by a write period length detection circuit 1, compared with a reference value and if the number of horizontal synchronizing signal for a vertical synchronizing signal is number of capacity or over of a field memory 28 larger in capacity than that of the effective pattern, the write of a video data to the memory 26 is inhibited via a comparator circuit 3 and a Write enable signal generation inhibit circuit 6. The readout of the data is implemented at a double speed of the write speed while being inhibited similarly as required and fed to a display section, the flicker is reduced and even if the number of horizontal synchronizing signals for the vertical synchronizing signal is fluctuated at special reproduction of a VTR, the deterioration of the quality of picture is prevented.
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公开(公告)号：JPH0281596A
公开(公告)日：1990-03-22
申请号：JP23325588
申请日：1988-09-17
Applicant: SONY CORP
Inventor： NAITO HIDEFUMI , SARUGAKU TOSHIO , HOSHINO TAKANARI , TOKUHARA MASAHARU
Abstract: PURPOSE:To simplify a system by using a memory means for both noise reduction means, which eliminates noise with the use of the correlation of the field of a video signal, and flicker reduction means, which doubles field frequencies and decreases a surface flicker. CONSTITUTION:A noise reduction circuit 22 is made into a circulative type filter constitution, and it is repeatedly added with the use of a single filter memory 26. In the field memory 26, the signal is written by a write control signal VCLRO from a flicker reduction circuit 29, digital luminance data read and added by a read control signal VCLR2 are generally outputted through a digital/analog converting circuit 30 after noise reduction. The field memory 26 used for the noise reduction circuit 22 is shared with the field memory of the flicker reduction circuit 29. Thus, the whole system can be simplified, and costs can be reduced.
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公开(公告)号：JPH0229171A
公开(公告)日：1990-01-31
申请号：JP17962088
申请日：1988-07-19
Applicant: SONY CORP
Inventor： MOTOE HISASHI , KAWASHIMA HIROYUKI , TOKUHARA MASAHARU
Abstract: PURPOSE:To suppress dot disturbance without any inconvenience by inserting a filter to eliminate a chrominance signal component into a signal line for animation data when a vertical edge is to be detected by a vertical edge detector. CONSTITUTION:In the title signal processing circuit to form both still picture data and the animation data from a luminance signal Y separated in a Y/C separating circuit composed of a tandem filter using line correlation and execute processing for obtaining high picture quality such as scanning line incorporation, the signal processing circuit is equipped with a vertical edge detector 519 and filters 515 and 516 to eliminate the chrominance signal component, and when the vertical edge is to be detected, the filters 515 and 516 to eliminate the chrominance signal component are inserted into the signal line for the animation data. Consequently, the chrominance signal component included in the animation data is eliminated correspondingly to a vertical edge part. Thus, the dot disturbance can be suppressed without any inconvenience.
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Patent Agency Ranking
公开(公告)号：JPH0229170A
公开(公告)日：1990-01-31
申请号：JP17961888
申请日：1988-07-19
Applicant: SONY CORP
Inventor： MOTOE HISASHI , MOTOMIYA MASAYUKI , KAWASHIMA HIROYUKI , TOKUHARA MASAHARU
IPC: H04N5/14
Abstract: PURPOSE:To minimize a circuit scale and to execute satisfactory Y/C separation and high picture quality processing all the time by providing an analog Y/C separating circuit, supplying a clock phase-locked with a horizontal synchronizing signal, and executing processing such as scanning line interpolation. CONSTITUTION:A luminance signal Y outputted from a Y/C separating circuit 2 is converted into a digital signal in an A/D converter 3Y and after that supplied to a signal processing circuit 5Y, a chrominance signal C is color- demodulated in a chroma decoder 4, converted into the digital signal in an A/D converter 3C, and after that supplied to a signal processing circuit 5C, signal processing such as the scanning line interpolation is executed, and both the luminance signal Y and the chrominance signal C are respectively made into analog signals in D/A converters 6Y, 6R and 6B. Further, a clock CLKH phase-locked with a horizontal synchronizing signal HD is outputted from a generating circuit 7, and this clock CLKH is supplied to a digital processing system composed from the A/D converters 3Y and 3C to the D/A converters 6Y, 6R and 6B. Thus, the circuit scale can be minimized, and the satisfactory Y/C separation and the processing for obtaining high picture quality can be executed all the time.
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公开(公告)号：JPS6446375A
公开(公告)日：1989-02-20
申请号：JP20264087
申请日：1987-08-14
Applicant: SONY CORP
Inventor： SONODA YUTAKA , YUJI HIROFUMI , MURAKAMI KYOICHI , TOKUHARA MASAHARU
Abstract: PURPOSE:To prevent the turblence of a picture from being generated due to a passing phenomenon by separating a reading address or a writing frame for the unit of frames or fields when the reading address and the writing address mutually pass. CONSTITUTION:An image memory 13 have memory capacity equivalent to four frames or for frames more than four to which an access is successively executed in a prescribed order. It is detected by passing detecting means 42 and 43 that a condition, in which the frame read by a reading address signal RADR and the frame written by a writing address signal WADR are mutually adjoined, is obtained. In correspondence to detecting outputs S21 and S22 of these passing detecting means 42 and 43, the writing address designated by the writing address signal WADR or the reading address designated by the reading address signal RADR is separated for one frame or plural frames by address separating means 41 and 44. Thus, the turbulence on the display image is prevented from being generated.
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公开(公告)号：JPS6229951B2
公开(公告)日：1987-06-29
申请号：JP3840677
申请日：1977-04-04
Applicant: SONY CORP
Inventor： MOTOMYA MASAYUKI , TOKUHARA MASAHARU , YAMAMOTO YOSHIHIRO , KAWAKAMI HIROMI
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公开(公告)号：JPS6227594B2
公开(公告)日：1987-06-16
申请号：JP949679
申请日：1979-01-30
Applicant: SONY CORP
Inventor： MOTOMYA MASAYUKI , TOKUHARA MASAHARU , OOMURO SHIGERU
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公开(公告)号：JPS62105584A
公开(公告)日：1987-05-16
申请号：JP24582585
申请日：1985-11-01
Applicant: SONY CORP
Inventor： SARUGAKU TOSHIO , MOTOE HISAFUMI , TOKUHARA MASAHARU , MOTOMIYA MASAYUKI
Abstract: PURPOSE:To facilitate the change and the selection of the type of a memory by constituting the picture memory by the plural memories equal in the number of secondary screens and adding a secondary screen selecting signal to a writing address signal and a reading address signal. CONSTITUTION:A signal for a main screen obtained from a changeover circuit 5 is applied to a Y/C processing and synchronization processing circuit 6 and the signal for the secondary screen is applied to a Y/C processing and synchronization processing circuit 7. The secondary screen signal obtained from the circuit 7 synchronizes with a synchronizing signal of the secondary screen signal, written in the memory 10 and the secondary screen signal is read synchronously with the synchronizing signal of the main screen signal from the memory 10. The memory 10 is constituted of for instance, four memories 10B-10E which are equal in the number of the secondary screens, and to the memories 10B-10E, common horizontal addresses 0-31, and vertical addresses 0-63 are applied. Screen selecting switches 21A-21E are provided, in accordance with a selecting operation, the screen selecting signal is applied to a control circuit 19 and a memory control circuit 13 from a screen selecting circuit 22. Thereby the screen can easily be selected.
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