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    SENSE AMPLIFIER WITH ZERO POWER IDLE MODE
    92.
    发明申请
    SENSE AMPLIFIER WITH ZERO POWER IDLE MODE 审中-公开
    具有零功率空闲模式的感应放大器

    公开(公告)号：WO99054880A1

    公开(公告)日：1999-10-28

    申请号：PCT/US1999/006807

    申请日：1999-03-29

    IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

    CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/1036

    Abstract: A sense amplifier (200) for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controlled manner (270), in response to a control pulse (SAEN). The control pulse (SAEN) is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps (200) are utilized to read out in parallel fashion the N memory cells (bits) comprising an accessed memory location. The sense amps (200) are therefore active only of a period of time sufficient to read out a memory cell.

    Abstract translation: 用于串行配置存储器的读出放大器（200）响应于控制脉冲（SAEN）包括以受控方式启用和禁用的多个级（270）。 在外部提供的时钟信号的每第N个周期产生控制脉冲（SAEN），所述时钟用于对表示存储器件内容的位流进行时钟输出。 在优选实施例中，N个这样的感测放大器（200）用于以并行方式读出包括访问的存储器位置的N个存储器单元（位）。 因此，感测放大器（200）仅在足以读出存储器单元的时间段内被激活。

    AN IMPROVED MEMORY ARCHITECTURE AND DEVICES, SYSTEMS AND METHODS UTILIZING THE SAME
    93.
    发明申请
    AN IMPROVED MEMORY ARCHITECTURE AND DEVICES, SYSTEMS AND METHODS UTILIZING THE SAME 审中-公开
    改进的存储器架构和使用其的设备，系统和方法

    公开(公告)号：WO1996008810A1

    公开(公告)日：1996-03-21

    申请号：PCT/US1995012088

    申请日：1995-09-11

    Applicant: CIRRUS LOGIC, INC.

    Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan

    IPC: G09G01/16

    CPC classification number: G11C7/1036

    Abstract: A memory (200) is provided which includes a plurality of self-contained memory units (201) for storing data. A plurality of shift registers (211) are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units (201). Interconnection circuitry (212) is coupled to a parallel data port of each of the shift registers. Control circuitry (208, 213) is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry (212) via the shift register (211) coupled to the selected memory unit (201).

    Abstract translation: 提供了一种存储器（200），其包括用于存储数据的多个独立存储单元（201）。 提供了多个移位寄存器（211），每个移位寄存器包括耦合到相应的一个独立存储单元（201）的数据端口的第一并行端口。 互连电路（212）耦合到每个移位寄存器的并行数据端口。 提供控制电路（208,213），其可操作以经由耦合到所选择的存储器单元（201）的移位寄存器（211）来控制存储器单元和互连电路（212）中的所选择的一个之间的数据交换。

    KR102225314B1 - Semiconductor Apparatus and Operation Method
    94.
    发明专利
    KR102225314B1 - Semiconductor Apparatus and Operation Method 有权

    公开(公告)号：KR102225314B1

    公开(公告)日：2021-03-10

    申请号：KR1020140160070A

    申请日：2014-11-17

    Applicant: 에스케이하이닉스 주식회사

    Inventor： 조호성

    IPC: G11C29/00 ,  G11C7/00

    CPC classification number: G11C7/1036 ,  G06F13/4068 ,  G11C7/1051 ,  G06F13/4282 ,  G06F9/30105 ,  G06F9/30134 ,  G11C16/32 ,  G11C29/1201 ,  G11C7/1078 ,  G11C7/22 ,  H03M9/00 ,  G11C16/10

    Abstract: 쉬프트 제어 신호, 및 캡쳐 제어 신호에 응답하여 직렬 형태의 입력 데이터를 병렬 형태의 제 1 데이터 세트 및 제 2 데이터 세트로서 출력하거나, 레지스터 선택 출력 신호를 상기 제 1 및 제 2 데이터 세트로서 출력하는 레지스터 입력 선택부; 제 1 업데이트 신호에 응답하여 상기 제 1 데이터 세트를 입력 받아 저장하고, 저장된 데이터를 제 1 레지스터 출력 신호로서 출력하는 제 1 데이터 레지스터; 제 2 업데이트 신호에 응답하여 상기 제 1 및 제 2 데이터 세트를 입력 받아 저장하고, 저장된 데이터를 제 2 레지스터 출력 신호로서 출력하는 제 2 데이터 레지스터; 선택 신호에 응답하여 상기 제 1 및 제 2 레지스터 출력 신호 중 하나를 상기 레지스터 선택 출력 선택 신호로서 출력하는 레지스터 출력 선택부; 및 상기 선택 신호에 응답하여 상기 제 1 및 제 2 데이터 세트 중 하나를 직렬 형태의 출력 데이터로서 출력하는 데이터 출력 선택부를 포함한다.

    Memory device
    97.
    发明专利
    Memory device 有权
    内存设备

    公开(公告)号：JP2011175688A

    公开(公告)日：2011-09-08

    申请号：JP2010036994

    申请日：2010-02-23

    Applicant: On Semiconductor Trading Ltd ,  オンセミコンダクター・トレーディング・リミテッド

    Inventor： RAI TOSHIKI ,  YOSHIKAWA SADAO

    IPC: G11C16/06 ,  G11C16/02 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C7/1036 ,  G11C7/08

    Abstract: PROBLEM TO BE SOLVED: To achieve a high read-out rate of data while suppressing an increase in circuit size in a serial interface memory device. SOLUTION: An EEPROM (Electrically Erasable PROM) 100 includes: a memory cell array 10 storing data; a row address decoder 11 and a column address decoder 12 that select an address of the memory cell array 10 according to an address signal serially input in synchronization with a clock; sense amplifiers SA0 to SA5, SA_M0, and SA_M1 each provided in association with each bit of the data; and a shift register 15 that outputs data read out from the sense amplifiers serially from a first bit in synchronization with the clock. The column address decoder 12 commences reading out two candidate data for the first bit by inputting the two candidate data to the sense amplifiers SA_M0 and SA_M1, respectively before all bits of the column address signal are established. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：为了在抑制串行接口存储器件中的电路尺寸的增加的同时实现高数据读出速率。 解决方案：EEPROM（电可擦除PROM）100包括：存储单元阵列10，存储数据; 行地址解码器11和列地址解码器12，其根据与时钟同步串行输入的地址信号选择存储单元阵列10的地址; 读出放大器SA0至SA5，SA_M0和SA_M1，每个与数据的每个位相关联地提供; 以及移位寄存器15，其与时钟同步地从第一位串行地输出从读出放大器读出的数据。 列地址解码器12分别在建立列地址信号的所有位之前，将两个候选数据分别输入到读出放大器SA_M0和SA_M1，开始读出第一位的两个候选数据。 版权所有（C）2011，JPO＆INPIT

    Semiconductor storage device
    99.
    发明专利
    Semiconductor storage device 审中-公开

    公开(公告)号：JP2004127449A

    公开(公告)日：2004-04-22

    申请号：JP2002292408

    申请日：2002-10-04

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： MATSUDERA KATSUKI ,  YONETANI KAZUHIDE ,  HISADA TOSHIKI ,  KOYANAGI MASARU

    IPC: G11C11/413 ,  G11C7/10 ,  G11C8/02 ,  G11C11/417 ,  H03M9/00

    CPC classification number: G11C7/1036

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device which provides the timing of a signal for controlling a read register and a write register with flexibility and has a function for changing data sequences. SOLUTION: The device is equipped with a memory core part 2, an I/O circuit 4 for inputting and outputting serial data, shift register parts 3 having the read register for receiving serial data of a plurality of bits from the I/O circuit 4 and converting the serial data into parallel data, and the write register for receiving parallel data of a plurality of bits from the memory core part 2 and converting the parallel data into serial data, and a signal generation circuit 6A for generating a plurality of first control signals that give conversion timing for each bit at the time of serial/parallel conversion and generating a plurality of second control signals that give conversion timing for each bit at the time of parallel/serial conversion. The signal generation circuit 6A controls rise or fall timing of the plurality of first and second control signals. COPYRIGHT: (C)2004,JPO

    Semiconductor memory
    100.
    发明专利
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：JPS6194295A

    公开(公告)日：1986-05-13

    申请号：JP21678584

    申请日：1984-10-16

    Applicant: Fujitsu Ltd

    Inventor： OGAWA JUNJI

    IPC: G11C7/00 ,  G11C7/10 ,  G11C11/40 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/41

    CPC classification number: G11C7/1036 ,  G11C7/1006 ,  G11C11/4096

    Abstract: PURPOSE: To solve the incapability of the 1-bit shift produced when the working speed is increased with a VRAM incorporating the shift register of the 1-word segment containing the master-slave constitution of each stage, by dividing the shift register into plural columns.
    CONSTITUTION: Transfer gates T
    3 and T
    4 are added to attain the connection of odd colum SR1, SR3,... and even column SR2, SR4,... of a shift register to the odd and even bit lines respectively. In the same way, the dummy cells DC are also connected to the odd and even bits. The transfer gates T
    1 WT
    4 are selected by exclusive transfer clocks TR1 and TR2. That is, the gates T
    3 and T
    4 are turned on by setting clocks TR2 and TR1 at H and L respectively. Then the odd bit lines are connected to columns SR2, SR4,... together with the even bit lines connected to columns SR1, SR3,... respectively (reverse mode). Thus the incapability of the 1-bit shift can be solved in said reverse mode.
    COPYRIGHT: (C)1986,JPO&Japio

    Abstract translation: 目的：为了解决当使用包含每级的主从构成的1字段的移位寄存器的VRAM增加工作速度时产生的1位移位的无效，通过将移位寄存器分成多列 。 构成：添加传输门T3和T4，以分别实现移位寄存器的奇数列SR1，SR3，...以及偶数列SR2，SR4，...与奇数和偶数位线的连接。 以同样的方式，虚拟单元DC也连接到奇数和偶数位。 传输门T1-T4由专用传输时钟TR1和TR2选择。 也就是说，通过将时钟TR2和TR1分别设置为H和L来使门T3和T4导通。 然后，奇数位线分别连接到列SR2，SR4，...以及连接到列SR1，SR3 ...的偶数位线（反向模式）。 因此，可以在所述反向模式中解决1位移位的无能力。

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