公开(公告)号：JPH05289975A

公开(公告)日：1993-11-05

申请号：JP1762993

申请日：1993-02-04

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU DEI JIEFUAADO ,  ANDORIYUU MATSUKUBURAIDO

IPC: G06F13/14 ,  G06F13/40

Abstract: PURPOSE: To provide a method and device which manage communication in a computing system. CONSTITUTION: A processor 32 and plural peripheral devices 40a to 40b are included. Information from plural places in a computing system 30 is received, and an activating profile is determined in accordance with a preliminarily determined reference. The activating profile is monitored to generate a feedback signal which logically handles the activating profile and indicates it. It is discriminated whether transfer trapping training should be used or not in response to the feedback signal, and thereby, transfer preliminarily determined for an inactivated peripheral device is stored until the inactivated device is activated.

公开(公告)号：JPH05250159A

公开(公告)日：1993-09-28

申请号：JP25014592

申请日：1992-09-18

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TAN MIN TORAN

IPC: G06F5/10 ,  G06F5/12 ,  G06F7/74 ,  G06F9/38

Abstract: PURPOSE: To solve data dependence among plural instructions in a storage device like a reorder buffer. CONSTITUTION: Each time the destination indicator of the instruction first stored in the storage device is matched with a source indicator in the instruction to be next sent, a comparator circuit 42 generates a comparison hit signal D. A 1st enable circuit 66 generates a 1st enable signal C for the instruction of a 1st packet specified by read and write pointers. Concerning the match of the comparison hit signal D and the 1st enable signal C, a 1st AND circuit 50 generates a hit enable signal E. Concerning the instruction of a 2nd packet specified by the read pointer and the hit enable signal E, a 2nd enable circuit 80 generates a 2nd enable signal F. Concerning the match of the 2nd enable signal F and the hit enable signal E, a 2nd AND circuit 86 generates an output signal G.

公开(公告)号：JPH05243970A

公开(公告)日：1993-09-21

申请号：JP18847192

申请日：1992-07-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BARII JIEI ROBINSON

IPC: G05F3/26 ,  H03F3/343 ,  H03K19/086

Abstract: PURPOSE: To provide an improved low voltage current mirror terminal circuit whose manufacture and assembly are comparatively simple and economical and which conquers the defect of the terminal circuit of preceding technology. CONSTITUTION: A low voltage current mirror terminal circuit used with an ECL gate array provides independent constant output emitter follower reference current (Ief) from a voltage change in a different output emitter follower power source (VEF). Current passing through the collector of a lateral direction PNP transistor (Qp) regulates mirror current (Ip). The base of the lateral direction transistor (Qp) is connected so that base bias voltage VEP is to be received. Current passing through the collector of a pull down transistor (Qf) regulates constant output emitter follower reference current (Ief) proportional to mirror current (Ip). The different emitter follower power source (VEF) has voltage lower than a power source (VEE) so that power consumption is reduced much.

公开(公告)号：JPH05216698A

公开(公告)日：1993-08-27

申请号：JP18139592

申请日：1992-07-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUTEIIBUN BII SHIDOMAN ,  BURENDAN JIEI BATSUBU

IPC: G06F11/10 ,  H03M13/15

Abstract: PURPOSE: To apply new approach for the error correction of an inspection bit in an encoded data word. CONSTITUTION: When a single error is generated in a word arranged in an inspection bit, the inspection bit generated by an inspection bit generator 14 is stored, and the newly generated inspection bit is outputted to a memory 12 by an inspection bit output latch 16. Data are exact, the newly generated inspection bit is also exact, and when the data are latched out, the inspection bit can be simultaneously latched out to the memory 12. This circuit includes a syndrome generator 18, error corrector 34, and error detector 36, and when the error is not detected in the data word, the inspection bit in the memory is corrected by the newly generated inspection bit. Thus, the performance of an error detecting and correcting circuit can be improved.

公开(公告)号：JPH0591721A

公开(公告)日：1993-04-09

申请号：JP7141891

申请日：1991-04-04

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ANTONIO JIEI MONTARUBO

IPC: H02M3/07

Abstract: PURPOSE: To obtain a charge pump circuit in which the output can reach a level higher than the breakdown voltage of oxide between the gate terminal and the source-drain terminal of an MOS capacitor. CONSTITUTION: The charge pump comprises a first MOSFET capacitor C1 (pumping operation capacitor), two other MOSFET capacitors C3 , C4 (back- to-back capacitor) connected together with the common joint of back-to-back capacitors connected in series with the pumping operation capacitor, a voltage clamp M1 connected with the common node of all three MOSFET capacitors, and a diode 350 for outputting through a pumping operation. A large number of these charge pump circuits may be cascaded to form a multistage charge pump circuit. Each charge pump circuit may reach an output voltage higher than the oxide breakdown voltage of the individual MOS capacitor.

公开(公告)号：JPH0588905A

公开(公告)日：1993-04-09

申请号：JP1362892

申请日：1992-01-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TERII JII RITSUTSU

IPC: G06F9/445 ,  G06F9/24 ,  G06F11/28

Abstract: PURPOSE: To obtain a microcomputer including a static RAM for internally storing program instructions and a program interface for obtaining the program instructions from an external source and storing the program instructions in this static RAM. CONSTITUTION: The microcontroller 10 of a type including an execution unit 20 for executing the stored program instructions consists of a memory system 12 for storing the program instructions and including a memory means for storing the program instructions, a memory means including the static RAM 14 and the program interface means 16 which is coupled to the static RAM 14 and is arranged so as to couple to the external source of the program instructions and programs the static RAM 14 by applying the program instructions from the external source for the program instructions to the static RAM 14.

公开(公告)号：JPH057799B2

公开(公告)日：1993-01-29

申请号：JP50411184

申请日：1984-10-22

Applicant: ADVANCED MICRO DEVICES INC

Inventor： UON TOOMASU ESU DABURYU

IPC: G11C11/34 ,  G11C7/06 ,  G11C11/416 ,  H03F3/45 ,  H03K3/286 ,  H03K5/12 ,  H03K5/24

公开(公告)号：JPH0514333A

公开(公告)日：1993-01-22

申请号：JP26227691

申请日：1991-10-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIYON EMU UINKUN

IPC: H03L7/08 ,  H03K3/03 ,  H03L7/089 ,  H04L7/033 ,  H04L25/49

Abstract: PURPOSE: To provide a receiver with the phase locked loop of a device for extracting a buried clock in the flow of data which is Manchester-encoded and with metal oxide semiconductor structure. CONSTITUTION: A multiplexer 14 selects the output of a receiver 16 or external clock reference 20. The external reference is the 10MHz signal of plus or minus 0.01%. VCO 34 drives a one shot and timing circuit. At output frequency is scaled by a scaling circuit 36 and is fed back to a phase frequency detector 30. The scaling circuit 36 is a four-division circuit. A control line is used for stopping the operation of VCO 34 and the scaling circuit and for initialization. The phase locked loop 12 is speedily locked to preamble before the data part of a packed which is Manchester-encoded reaches. When a data packet completes, the external reference clock 20 is selected again.

公开(公告)号：JPH053950B2

公开(公告)日：1993-01-18

申请号：JP50327784

申请日：1984-08-17

Applicant: ADVANCED MICRO DEVICES INC

Inventor： RARAPARI KURISHUNA ,  KAKU SHINKYOO

IPC: H04N1/417 ,  G06T9/00 ,  H03M7/46 ,  H04N1/419 ,  H04N7/12

公开(公告)号：JPH0481840B2

公开(公告)日：1992-12-25

申请号：JP50127884

申请日：1984-02-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURAUN JOOJI DABURYU ,  TAAII FUAI

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24