COMPOSITE CALIBRATION PLATE
    101.
    发明公开

    公开(公告)号:US20240219229A1

    公开(公告)日:2024-07-04

    申请号:US18400686

    申请日:2023-12-29

    Inventor: Chien-Hsun CHU

    CPC classification number: G01J1/4228 C12Q1/6848

    Abstract: A composite calibration plate includes a control board, a light detection board, a diffusion board, a light-emitting sheet, and a fluorescent sheet. The control board has a first setting surface and a second setting surface. The light detection board is stacked on the first setting surface. The diffusion board is stacked on the light detection board. The light-emitting sheet is stacked on the second setting surface and includes a plurality of self-luminous sources. The fluorescent sheet is optionally stacked on the light-emitting sheet or the diffusion board, and has a plurality of fluorescent chips. When calibrating the lighting device, the fluorescent sheet is disposed on the light-emitting sheet; and, when calibrating the imaging device, the fluorescent sheet is disposed on the light-emitting sheet, such that the fluorescent sheet is located at a focus position of an optical imaging path.

    CONTAINMENT APPARATUS FOR BATTERY TRAY RACK
    102.
    发明公开

    公开(公告)号:US20240194926A1

    公开(公告)日:2024-06-13

    申请号:US18516682

    申请日:2023-11-21

    CPC classification number: H01M10/0404

    Abstract: A containment apparatus for battery tray rack includes a pressing module, a securing module, and a controller. In response to that the containment apparatus is to form the containment on the battery tray rack, the controller controls the pressing module to apply a compressive force, so that the battery tray rack withstands a clamping pressure, and the controller controls the securing module to lock the battery tray rack to maintain the clamping pressure. In response to that the containment apparatus is to release the containment from the battery tray rack, the controller controls the pressing module to apply the compressive force, and the controller controls the securing module to unlock the battery tray rack, and then the controller controls the pressing module to cancel the compressive force.

    POGO PIN COOLING SYSTEM AND METHOD AND ELECTRONIC DEVICE TESTING APPARATUS HAVING THE SYSTEM

    公开(公告)号:US20240142492A1

    公开(公告)日:2024-05-02

    申请号:US18050500

    申请日:2022-10-28

    CPC classification number: G01R1/0466 G01R31/2877

    Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.

    Wafer inspection method and inspection apparatus

    公开(公告)号:US11841381B2

    公开(公告)日:2023-12-12

    申请号:US17950467

    申请日:2022-09-22

    CPC classification number: G01R1/07385 G01R1/06766 G01R1/28 G01R31/318511

    Abstract: A wafer inspection method and inspection apparatus are provided. On a wafer having layout lines connecting electrode points of individual dies in series, the dies within a matrix range are inspected one after another in turn in a column/row control means by a first switch group and a second switch group of a probe card, so that each die is selectively configured in a test loop of a test process by turning on/off of a corresponding switch. Thus, after inspection of a die under inspection (a selected die) within the matrix range is complete, the column/row control means is used to switch to a next die to achieve fast switching. Accordingly, for the inspection procedure of each die within the matrix region, a conventional procedure of moving one after another in turn can be eliminated, significantly reducing the total test time needed and enhancing inspection efficiency.

    Method and apparatus for testing a package-on-package semiconductor device

    公开(公告)号:US20230349968A1

    公开(公告)日:2023-11-02

    申请号:US18299173

    申请日:2023-04-12

    CPC classification number: G01R31/2896 G01R31/2887 G01R31/2893

    Abstract: The present invention relates to an apparatus for testing a package-on-package semiconductor device, mainly comprising a pick-and-place device, a test socket, an upper chip holder, and a main controller. When a first package device is to be tested, the main controller controls the pick-and-place device to load the first package device into the test socket and then controls the pick-and-place device to transfer the upper chip holder and bring the upper chip holder into electrical contact with the first package device on the test socket so that a second package device in the upper chip holder is electrically connected to the first package device for testing. Accordingly, the upper chip holder is an independent component. Only when a test is executed, the pick-and-place device transfers the upper chip holder onto the test socket so that the second package device is electrically connected to the first package device.

    INTEGRATED POWER SYSTEM CAPABLE OF SWITCHING BETWEEN POWER SUPPLY MODE AND ELECTRONIC LOAD MODE AND SWITCHING METHOD THEREOF

    公开(公告)号:US20230134013A1

    公开(公告)日:2023-05-04

    申请号:US17938055

    申请日:2022-10-05

    Abstract: Systems and methods for switching between a power supply mode and an electronic load mode are disclosed. For switching from the power supply mode to the electronic load mode, the method comprises the steps of: deactivating a power element; activating a current control module and a phase-locked loop to obtain a voltage phase of a device under test; calculating a turn-on amount of the power element according to a current setting value and the voltage phase; and causing the power element to generate a load current for the device under test. For switching from the electronic load mode to the power supply mode, the method comprises the steps of: deactivating the power element; activating a voltage control module; calculating the turn-on amount of the power element according to a voltage setting value; and causing the power element to input a corresponding voltage to the device under test.

    OPTICAL INSPECTION APPARATUS IN SEMICONDUCTOR PROCESS SYSTEM

    公开(公告)号:US20220208618A1

    公开(公告)日:2022-06-30

    申请号:US17562238

    申请日:2021-12-27

    Abstract: The present invention discloses an optical detection apparatus for defining a detection surface on a carrier unit for a wafer in a semiconductor manufacturing process so as to obtain a corresponding detection image, wherein a vertical movement path for another device to move is defined above the carrier unit. The optical detection apparatus includes a support, and an imaging device disposed on the support and configured to be non-interfering with the movement path. The imaging device includes a lens group, an image capturing portion and a moving base. With the moving base, the photosensitive element of the image capturing portion is allowed to move horizontally relative to the lens group, and the imaging position can be adjusted, preventing image deformation or a reduced resolution easily caused by capturing at an oblique angle. Thus, the optical detection apparatus resolves complications of additionally mounting an optical detection apparatus in an optical detection environment within a narrow space.

    ELECTRONIC LOAD APPARATUS
    109.
    发明申请

    公开(公告)号:US20220206080A1

    公开(公告)日:2022-06-30

    申请号:US17371976

    申请日:2021-07-09

    Abstract: The present disclosure relates to an electronic load apparatus. An embodiment of the present disclosure includes an electronic load apparatus including: a measurement resistor, a reference circuit, a transistor, and a feedback circuit. The measurement resistor includes a first contact, a second contact, a third contact, and a fourth contact. The first contact and the second contact are located at a first end of the measurement resistor. The third contact and the fourth contact are located at a second end of the measurement resistor. A reference power (or a reference voltage) electrically connects to the reference circuit. The reference circuit and the first contact of the measurement resistor are electrically connected. The transistor includes a drain, a gate, and a source. The reference circuit and the gate of the transistor are electrically connected. One of the source and the drain of the transistor electrically connects to the second contact of the measurement resistor. The other one of the drain and the source of the transistor electrically connects to an output terminal of a unit under test. The feedback circuit and the fourth contact of the measurement resistor are electrically connected. The feedback circuit and the reference circuit are electrically connected.

    Condensing system
    110.
    发明授权

    公开(公告)号:US11300491B2

    公开(公告)日:2022-04-12

    申请号:US16676458

    申请日:2019-11-07

    Abstract: A condensing system is used to generate a condensing layer on a surface of a test object. The condensing system includes airflow generating device and a passage device. The airflow generating device is used to generate condensing airflow. The condensing airflow has a dew point higher than a temperature of the surface of the test object. The passage device is connected to the airflow generating device, and the condensing airflow flows from the airflow generating device into the passage device. The passage device includes a flow-uniforming module. The flow-uniforming module includes at least one uniforming board. Each of the at least one uniforming board has at least a first hole.

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