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    SIGNAL PROCESSOR UNIT AND COMMUNICATION DEVICE
    101.
    发明公开
    SIGNAL PROCESSOR UNIT AND COMMUNICATION DEVICE 有权
    信号检测在KOMMUNIKATIONSEINRICHTUNG

    公开(公告)号：EP2207308A1

    公开(公告)日：2010-07-14

    申请号：EP07831164.4

    申请日：2007-11-02

    Applicant: Fujitsu Microelectronics Limited

    Inventor： SHIMAMURA, Akira ,  MITA, Koichi ,  ARAI, Takashi ,  FUJISHIMA, Hideshi ,  ENDO, Akira

    IPC: H04L12/28

    CPC classification number: H04J3/06 ,  H04L12/40006 ,  H04L12/40032 ,  H04L2012/40241

    Abstract: A signal processor related to frame communication which is proceeded based on allocated unit communication periods, in which each communication device recognizes the end of communication of a frame based on a received signal, and then starts a communication action of the next frame, the signal processor has a period detection section which detects that a period is currently used for communication of a frame; a pattern detection section which detects, from the received signal, a first signal pattern by which the end of communication of the frame is recognized; and an output processing section which outputs the received signal to a controller connected thereto, configured to instruct, upon detection of the first signal pattern in the period being currently used for communication of a frame, the controller to halt startup of communication action of the next frame, until the period being currently used for communication of a frame comes to the end, to thereby prevent an event such that frames are transmitted from a plurality of communication devices simultaneously, and to thereby allow the communication action for the next frame to proceed correctly.

    Abstract translation: 一种与帧通信相关的信号处理器，其基于分配的单元通信周期进行，其中每个通信设备基于接收到的信号识别帧的通信结束，然后开始下一帧的通信动作，信号处理器 具有周期检测部，其检测当前用于帧的通信的周期; 模式检测部分，从接收到的信号中检测识别帧的通信结束的第一信号模式; 以及输出处理部，其将接收到的信号输出到与其连接的控制器，其被配置为在当前用于帧的通信的时段中检测到第一信号模式时指示，所述控制器停止启动下一个的通信动作 直到当前用于帧的通信的时间段结束为止，从而防止从多个通信设备同时发送帧的事件，从而允许下一帧的通信动作正确地进行 。

    Phase detector circuitry
    104.
    发明公开
    Phase detector circuitry 审中-公开
    Phasendetektorschaltung

    公开(公告)号：EP2187524A1

    公开(公告)日：2010-05-19

    申请号：EP08169190.9

    申请日：2008-11-14

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Marton, Walter ,  Braun, Robert

    IPC: H03L7/089

    CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/1806 ,  H03L7/193 ,  H03L7/1974

    Abstract: Phase detector circuitry for a phase-locked loop frequency synthesizer, the phase detector circuitry comprising
    a reference input configured to receive a reference signal;
    a feedback input configured to receive a divided signal from divider circuitry in a feedback path of the phase-locked loop; and
    pulse generation circuitry configured to generate control pulses for controlling a charge pump in the phase-locked loop in accordance with a frequency and phase relationship between the reference signal and the divided signal;
    wherein the divided signal comprises a pulse having a length shorter than a half period of the divided signal, and wherein the pulse generation circuitry is configured to generate the control pulses by masking the reference signal using the pulse of the divided signal as a mask, so as to define the edges of the control pulses from the edges of the divided signal and an edge of the reference signal.

    Abstract translation: 用于锁相环频率合成器的相位检测器电路，所述相位检测器电路包括被配置为接收参考信号的参考输入; 反馈输入，被配置为在锁相环的反馈路径中从分频器电路接收分频信号; 以及脉冲发生电路，其被配置为根据所述参考信号和所述分频信号之间的频率和相位关系产生用于控制所述锁相环中的电荷泵的控制脉冲; 其中分频信号包括长度短于分频信号的半周期的脉冲，并且其中脉冲发生电路被配置为通过使用分频信号的脉冲作为掩码来掩蔽参考信号来产生控制脉冲，因此 以便从划分的信号的边缘和参考信号的边缘定义控制脉冲的边缘。

    Semiconductor device and method for fabricating the same
    106.
    发明公开
    Semiconductor device and method for fabricating the same 有权
    Halbleitervorrichtung und Herstellungsverfahren

    公开(公告)号：EP2175486A2

    公开(公告)日：2010-04-14

    申请号：EP10000803.6

    申请日：2003-07-24

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Watanabe, Kenichi

    IPC: H01L23/522 ,  H01L23/532

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective fil ling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

    Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此，能够防止埋入导体的缺陷，能够防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

    Semiconductor memory
    108.
    发明公开
    Semiconductor memory 有权
    半导体内存

    公开(公告)号：EP2166540A1

    公开(公告)日：2010-03-24

    申请号：EP09169013.1

    申请日：2003-03-10

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Sasaki, Junichi ,  Shinozaki, Naoharu

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/103 ,  G11C7/1048 ,  G11C7/22 ,  G11C2207/002

    Abstract: A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder successively selects column selecting lines in synchronization with the column pulses. A plurality of bits of data read from memory cells in response to a single read command RD is successively transmitted to a common data bus line through column switches. This can reduce the number of data bus lines to a minimum, preventing an increase in chip size. Since a single data bus line can transmit a plurality of bits of data, it is possible to minimize the size of the memory region to be activated in response to a read command. This consequently allows a reduction in power consumption.

    Abstract translation: 脉冲发生器响应于读取命令而产生多个列脉冲。 地址计数器将连续读取命令提供的外部地址之后的地址连续地输出为内部地址。 列解码器连续地选择与列脉冲同步的列选择线。 响应于单个读取命令RD从存储器单元读取的多个数据位通过列开关被连续地发送到公共数据总线。 这可以将数据总线的数量减少到最少，从而防止芯片尺寸的增加。 由于单个数据总线可以传输多个数据位，所以可以响应于读取命令而最小化待激活的存储器区域的大小。 这因此可以降低功耗。

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