公开(公告)号：EP2706410A1

公开(公告)日：2014-03-12

申请号：EP13195857.1

申请日：2003-02-14

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  H01L23/00 ,  H01L23/58 ,  H01L21/768

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device, comprising: a substrate which includes a first edge region, an integrated circuit region surrounded by the first edge region in a plan view and a second edge region located between the first edge region and the integrated circuit region in a plan view; a first interlayer insulation film (116) formed above the substrate; a contact hole formed in the first interlayer insulation film of the integrated circuit region; a first trench (131) formed in the first interlayer insulation film of the first edge region; a second trench (131), which is connected to the first trench at two positions, formed in the first interlayer insulation film of the second edge region; a second interlayer insulation film (117) formed above the first interlayer insulation film; a third trench (132), which is wider than the first trench in a plan view and which is connected to the first trench, formed in the second interlayer insulation film of the first region; a fourth trench (132), which is wider than the second trench in a plan view, which is connected to the third trench at two position in a plan view and which is connected to the second trench, formed in the second interlayer insulation film of the second region; a fifth trench formed in the second interlayer insulation film of the integrated circuit region; and a first metal film (120a) formed in the contact hole, the first trench, the second trench, the third trench, the fourth trench and the fifth trench, the first edge region includes a main-wall part (2) which includes the first trench and the third trench, and the second edge region includes a first sub-wall part (3b) which includes the second trench and the fourth trench.

Abstract translation: 一种半导体器件，包括：在平面图中包括第一边缘区域，被所述第一边缘区域包围的集成电路区域和位于所述第一边缘区域和所述集成电路区域之间的第二边缘区域的基板; 形成在所述基板上方的第一层间绝缘膜（116） 形成在集成电路区域的第一层间绝缘膜中的接触孔; 形成在所述第一边缘区域的所述第一层间绝缘膜中的第一沟槽（131） 第二沟槽（131），其形成在所述第二边缘区域的所述第一层间绝缘膜中的两个位置处连接到所述第一沟槽; 形成在所述第一层间绝缘膜之上的第二层间绝缘膜; 第三沟槽（132），其在平面图中比所述第一沟槽宽，并且连接到所述第一沟槽，形成在所述第一区域的所述第二层间绝缘膜中; 在平面图中比第二沟槽宽的第四沟槽（132），其在平面图的两个位置处连接到第三沟槽，并且连接到形成在第二沟槽中的第二层间绝缘膜中 第二区; 形成在所述集成电路区域的第二层间绝缘膜中的第五沟槽; 以及形成在所述接触孔，所述第一沟槽，所述第二沟槽，所述第三沟槽，所述第四沟槽和所述第五沟槽中的第一金属膜（120a），所述第一边缘区域包括主壁部分（2） 第一沟槽和第三沟槽，并且第二边缘区域包括包括第二沟槽和第四沟槽的第一子壁部分（3b）。

公开(公告)号：EP2503390A2

公开(公告)日：2012-09-26

申请号：EP12173143.4

申请日：2003-02-14

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  G03F1/32 ,  H01L23/58 ,  H01L21/768

Abstract: A phase shift mask, comprising a phase shifter film (302) formed on a transparent substrate (300), and a light shield film (314) formed in a scribe line region (312) on said transparent substrate (300). A region surrounded by said scribe line region (312) is constituted of an integrated circuit region (304) with which an integrated circuit part is to be formed and a peripheral edge region (306) with which a peripheral edge part in a periphery of said integrated circuit part is to be formed. The light shield film (314) is further formed at least in a part of said peripheral edge region (306) and said integrated circuit region (304).

Abstract translation: 一种相移掩模，包括形成在透明基板（300）上的移相膜（302）和形成在所述透明基板（300）上的划线区域（312）中的遮光膜（314）。 由所述划线区域（312）围绕的区域由要形成集成电路部分的集成电路区域（304）和周边边缘区域（306）构成，周边区域 集成电路部分要形成。 至少在所述周缘区域（306）和集成电路区域（304）的至少一部分中进一步形成遮光膜（314）。

公开(公告)号：EP2264758A2

公开(公告)日：2010-12-22

申请号：EP10177318.2

申请日：2002-12-05

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Shimizu, Noriyoshi ,  Suzuki, Takashi

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device which comprises a second insulating film (29) formed on a substantially flat surface, on which a surface of a first wiring (36) and a surface of a first insulating film (95) are continued, to cover the first wiring (36), a wiring trench (28a) formed in the second insulating film (29), connection holes (38a) formed in the second insulating film (29) to extend from the wiring trench (28a) to the first wiring (36), dummy connection holes (38b) formed in the second insulating film (29) to extend from the wiring trench (28a) to a non-forming region of the first wiring, and a second wiring (39) buried in the connection holes (38a) and the wiring trench (28a) to be connected electrically to the first wiring (36) and also buried in the dummy connection holes (38b), and formed such that a surface of the second wiring (39) and a surface of the second insulating film (29) constitute a substantially flat surface.

Abstract translation: 提供了一种半导体器件，其包括形成在基本上平坦的表面上的第二绝缘膜（29），第一布线（36）的表面和第一绝缘膜（95）的表面在其上连续覆盖 第一布线（36），形成在第二绝缘膜（29）中的布线沟槽（28a），形成在第二绝缘膜（29）中的布线沟槽（28a）延伸到第一布线（ 36），形成在第二绝缘膜（29）中的从布线沟槽（28a）延伸到第一布线的非成形区域的虚设连接孔（38b）和埋在连接孔 （38a）和与第一布线（36）电连接并且还埋入虚拟连接孔（38b）中的布线沟槽（28a），并且形成为使得第二布线（39）的表面和 第二绝缘膜（29）构成基本平坦的表面。

公开(公告)号：EP2175487A2

公开(公告)日：2010-04-14

申请号：EP10000804.4

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

公开(公告)号：EP2175486A3

公开(公告)日：2012-03-28

申请号：EP10000803.6

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective fil ling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 该半导体器件包括：在衬底10上形成的绝缘膜40,42; 埋入绝缘膜40,42的至少一个表面侧的配线58; 绝缘膜60,62，形成在绝缘膜42上，并包括具有弯曲成直角图案的孔状通孔60和槽状通孔66a; 以及掩埋在孔状通孔60和槽状通孔66a中的掩埋导体70,72a，其中槽状通孔66a形成为具有小于孔的宽度的宽度 从而防止了埋入导体的缺陷填充，并且可以防止层间绝缘膜的破裂。 可以减少导体插头上的台阶，使得台阶不会影响上互连层和绝缘层。 因此，可以防止与上互连层的接触不良以及形成膜时发生的问题，并且因此半导体器件可以具有高水阻和高互连可靠性。

公开(公告)号：EP2204843A3

公开(公告)日：2010-07-21

申请号：EP10160546.7

申请日：2003-08-01

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Ikeda, Masanobu ,  Kimura, Takahiro

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L27/04 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L21/76838 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05546 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01004

Abstract: In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided.

Abstract translation: 在将元件形成区域与外部电连接的焊盘形成区域中，与元件形成区域相关地形成有低介电常数绝缘膜，在该低介电常数绝缘膜中形成作为通路的Cu膜 在元件形成区域中，焊盘形成区域以比用作通路的Cu膜更高的密度设置。 由此，当发生内部应力时，可以防止应力不均衡地集中在通路上，并且可以避免由此引起的布线功能的恶化。

公开(公告)号：EP2175487B1

公开(公告)日：2015-03-11

申请号：EP10000804.4

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

公开(公告)号：EP2503390A3

公开(公告)日：2013-01-09

申请号：EP12173143.4

申请日：2003-02-14

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  G03F1/32 ,  H01L23/58 ,  H01L21/768

Abstract: A phase shift mask, comprising a phase shifter film (302) formed on a transparent substrate (300), and a light shield film (314) formed in a scribe line region (312) on said transparent substrate (300). A region surrounded by said scribe line region (312) is constituted of an integrated circuit region (304) with which an integrated circuit part is to be formed and a peripheral edge region (306) with which a peripheral edge part in a periphery of said integrated circuit part is to be formed. The light shield film (314) is further formed at least in a part of said peripheral edge region (306) and said integrated circuit region (304).

公开(公告)号：EP2175487A3

公开(公告)日：2012-04-18

申请号：EP10000804.4

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

公开(公告)号：EP2264758A3

公开(公告)日：2012-01-25

申请号：EP10177318.2

申请日：2002-12-05

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Shimizu, Noriyoshi ,  Suzuki, Takashi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device which comprises a second insulating film (29) formed on a substantially flat surface, on which a surface of a first wiring (36) and a surface of a first insulating film (95) are continued, to cover the first wiring (36), a wiring trench (28a) formed in the second insulating film (29), connection holes (38a) formed in the second insulating film (29) to extend from the wiring trench (28a) to the first wiring (36), dummy connection holes (38b) formed in the second insulating film (29) to extend from the wiring trench (28a) to a non-forming region of the first wiring, and a second wiring (39) buried in the connection holes (38a) and the wiring trench (28a) to be connected electrically to the first wiring (36) and also buried in the dummy connection holes (38b), and formed such that a surface of the second wiring (39) and a surface of the second insulating film (29) constitute a substantially flat surface.