公开(公告)号：US20170236836A1

公开(公告)日：2017-08-17

申请号：US15503833

申请日：2014-09-25

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Zongliang HUO ,  Ming LIU ,  Lei JIN

IPC: H01L27/11582

CPC classification number: H01L27/11582 ,  H01L27/11578 ,  H01L28/00

Abstract: A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings. In accordance with the three-dimensional memory manufacturing method of the present invention, the deep trenches of word-line in the TCAT three-dimensional device are replaced with deep-hole etching to realize the same function, thereby improving the integration density, simplifying the etching process of stacked structure, and maintaining the control performance of the metal gate.

公开(公告)号：US09711409B2

公开(公告)日：2017-07-18

申请号：US14409527

申请日：2012-11-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/31055 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66795

Abstract: A fin arrangement and a method for manufacturing the same are provided. An example method may include: patterning a substrate to form an initial fin on a selected area of the substrate; forming, on the substrate, a dielectric layer to substantially cover the initial fin, wherein a portion of the dielectric layer located on top of the initial fin has a thickness substantially less than that of a portion the dielectric layer located on the substrate; and etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion of the initial fin is used as a fin.

公开(公告)号：US20170148881A1

公开(公告)日：2017-05-25

申请号：US15424642

申请日：2017-02-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/311 ,  H01L21/31105 ,  H01L21/76897 ,  H01L29/0638 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer.

公开(公告)号：US09601566B2

公开(公告)日：2017-03-21

申请号：US14439514

申请日：2012-11-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/28 ,  H01L21/30604 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.

公开(公告)号：US09583621B2

公开(公告)日：2017-02-28

申请号：US14797767

申请日：2015-07-13

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/3083 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

Abstract: Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a fin formed on a substrate; a gate stack formed on the substrate and intersecting the fin, wherein the gate stack is isolated from the substrate by an isolation layer, and a Punch-Through Stopper (PTS) formed under the fin, including a first section directly under a portion of the fin where the fin intersects the gate stack and second sections on opposite sides of the first section, wherein the second sections each have a doping concentration lower than that of the first section.

Abstract translation: 提供半导体器件及其制造方法。 示例性装置可以包括：形成在基板上的翅片; 形成在所述基板上并且与所述鳍片相交的栅极堆叠，其中所述栅极堆叠层通过隔离层与所述衬底隔离，以及形成在所述鳍片下方的穿通止动器（PTS），所述穿通止动器包括直接位于所述鳍片下方的第一部分 翅片，其中翅片与第一部分的相反侧的栅叠层和第二部分相交，其中第二部分各自具有低于第一部分的掺杂浓度。

公开(公告)号：US09577074B2

公开(公告)日：2017-02-21

申请号：US14905465

申请日：2013-10-22

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Yunfei Liu ,  Haizhou Yin ,  Keke Zhang

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7853

Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy. Some advantages of the current invention may be, harmful effects produced in the source/drain regions by the triangle fin structure are eliminated, the device performance is improved, and the complexity of the process is reduce.

Abstract translation: 提供一种制造FinFET器件的方法，包括：a。 提供衬底（100）; b。 在所述基板上形成翅片（200）; C。 在衬底上形成浅沟槽隔离结构（300）; d。 在所述隔离结构上形成牺牲栅极堆叠，其中所述牺牲栅极堆叠与所述鳍片相交; e。 通过离子注入形成源极/漏极掺杂区域; F。 在衬底上沉积层间电介质层（400）; G。 去除牺牲栅极堆叠以形成牺牲栅极空位; H。 在牺牲栅极空位下形成掺杂区域（201）; 一世。 在牺牲栅极空位下蚀刻浅沟槽隔离结构（300），直到浅沟槽隔离结构（300）的顶表面与源极/漏极掺杂区域的底表面一致; j。 在牺牲栅极空位中形成新的栅极堆叠。 本发明的一些优点可以是消除由三角鳍结构在源极/漏极区域产生的有害影响，提高了器件性能，并且降低了工艺的复杂性。

公开(公告)号：US09536585B2

公开(公告)日：2017-01-03

申请号：US14904979

申请日：2014-05-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Mengxin Liu ,  Xin Liu ,  Fazhan Zhao ,  Zhengsheng Han

IPC: G11C11/34 ,  G11C11/419

CPC classification number: G11C11/34 ,  G11C11/412 ,  G11C11/419

Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved SRAM memory cell based on a DICE structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current SRAM storage cells based on a DICE structure can easily be affected by the electrical level of storage nodes. This effectively improves reliability of storage cells.

Abstract translation: 本发明提供了一种基于DICE结构的改进的SRAM存储单元，其包括以下结构：通过串联布置PMOS晶体管和NMOS晶体管而形成的四个反相器结构，其中PMOS晶体管的漏极和NMOS晶体管之间的部分用作 存储节点; 每个存储节点控制另一个逆变器结构的NMOS晶体管的栅极电压和另一个反相器结构的PMOS晶体管的栅极电压; 由四个NMOS晶体管组成的传输结构，其源极，栅极和漏极分别与位线/位线条，字线和存储节点连接。 基于DICE结构的改进的SRAM存储单元的使用不仅避免了由6个晶体管组成的传统单元结构面临的小静态噪声容限和易发生传输错误等缺陷，而且解决了当前SRAM存储单元 基于DICE结构可以容易地受到存储节点电平的影响。 这有效地提高了存储单元的可靠性。

公开(公告)号：US09508776B2

公开(公告)日：2016-11-29

申请号：US14771145

申请日：2013-09-24

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi Liu ,  Ming Liu ,  Shibing Long ,  Hangbing Lv ,  Yan Wang

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/15 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/08 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/148

Abstract: A gating device cell for a cross array of bipolar resistive memory cells comprises an n-p diode and a p-n diode, wherein the n-p diode and the p-n diode have opposite polarities and are connected in parallel, such that the gating device cell exhibits a bidirectional rectification feature. The gating device cell exhibits the bidirectional rectification feature, that is, it can provide a relatively high current density at any voltage polarity in its ON state, and also a relatively great rectification ratio (Rv/2/RV) under a read voltage. Therefore, it is possible to suppress read crosstalk in the cross array of bipolar resistive memory cells to avoid misreading, thereby solving the problem that a conventional rectifier diode is only applicable to a cross array of unipolar resistive memory cells.

Abstract translation: 用于双极性电阻式存储单元的交叉阵列的门控器件单元包括np二极管和pn二极管，其中np二极管和pn二极管具有相反的极性并且并联连接，使得门控器件单元呈现双向整流特征 。 选通装置单元具有双向整流特征，即，其可以在其导通状态下的任何电压极性下提供相对高的电流密度，并且在读取电压下可以提供相对较大的整流比（Rv / 2 / RV）。 因此，可以抑制双极电阻存储单元的交叉阵列中的读串扰，以避免误读，从而解决了传统的整流二极管仅可应用于单极性电阻存储单元的交叉阵列的问题。

公开(公告)号：US20160329347A1

公开(公告)日：2016-11-10

申请号：US15214372

申请日：2016-07-19

Applicant: Institute of Microelectronics. Chinese Academy of Sciences

Inventor： Zongliang Huo ,  Ming Liu

IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/788 ,  H01L21/324 ,  H01L21/764 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.

Abstract translation: 公开了一种垂直沟道型3D半导体存储器件及其制造方法。 一方面，该方法包括在衬底上沉积交替的绝缘和电极层以形成多层膜。 该方法还包括将膜蚀刻到衬底上以形成通孔，每个通孔限定沟道区域。 该方法还包括依次在通孔的内壁上沉积屏障，存储和隧道层以形成栅极叠层。 该方法还包括在栅极堆叠的隧道层的表面上沉积和不完全填充沟道材料以形成中空通道。 该方法还包括在接触孔区域形成用于在中空通道的顶部部分进行位线连接的排水沟。 该方法还包括在中空通道的底部中的通孔和基板之间的接触区域中形成源。

公开(公告)号：US09461116B2

公开(公告)日：2016-10-04

申请号：US14649553

申请日：2012-12-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES ,  SHANGHAI LIANXING ELECTRONICS CO., LTD. ,  JIANGSU CAS-IGBT TECHNOLOGY CO., LTD

Inventor： Yangjun Zhu ,  Wenliang Zhang ,  Shuojin Lu ,  Xiaoli Tian ,  Aibin Hu

IPC: H01L29/739 ,  H01L21/331 ,  H01L21/425 ,  H01L21/302 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/36 ,  H01L21/18

CPC classification number: H01L29/0834 ,  H01L21/185 ,  H01L21/26513 ,  H01L21/302 ,  H01L29/0615 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/66333 ,  H01L29/7395

Abstract: A TI-IGBT, comprising a first semiconductor substrate, a second semiconductor substrate, and a first doped layer; a short circuit region and a collector region disposed in parallel are formed in the first semiconductor substrate; the short circuit region and the collector region have different doping types; the second semiconductor substrate is located on the upper surface of the first semiconductor substrate, and has the same doping type with the short circuit region; the first doped layer is located between the first semiconductor substrate and the second semiconductor substrate, and covers at least the collector region; the first doped layer has the same doping type with the second semiconductor substrate, and has a doping concentration smaller than that of the second semiconductor substrate.

Abstract translation: 一种TI-IGBT，包括第一半导体衬底，第二半导体衬底和第一掺杂层; 在第一半导体衬底中形成平行布置的短路区域和集电极区域; 短路区域和集电极区域具有不同的掺杂类型; 所述第二半导体衬底位于所述第一半导体衬底的上表面上，并且具有与所述短路区域相同的掺杂型; 所述第一掺杂层位于所述第一半导体衬底和所述第二半导体衬底之间，并且至少覆盖所述集电极区域; 第一掺杂层与第二半导体衬底具有相同的掺杂类型，并且其掺杂浓度小于第二半导体衬底的掺杂浓度。