公开(公告)号：JPH11238797A

公开(公告)日：1999-08-31

申请号：JP34933598

申请日：1998-11-25

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： GAYET PHILIPPE

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To obtain structure including the level of a conductor being separated by insulation layers that locally cross by a via being filled with metal, by including a stage for performing retching to the level of a surface at the upper side of a sacrifice layer by chemico-mechanical polishing after depositing metallization. SOLUTION: In a method for manufacturing metallization, the thickness of a dielectric layer 38 where the dielectric layer 38 that is made of a material that cannot be etched easily by a prescribed method, is formed on a support is satisfied based on a predetermined pattern. A sacrificial layer 32 with a desired thickness in a material layer is formed on a support 31, an opening 34 is formed at the sacrificial layer 32 based on a determined pattern, and metallization 35 is formed in the opening 34. Then, the sacrificial layer 32 is eliminated, and the layer of a material 37 which at least exceeding a thickness that is equal to that of a metal pattern is deposited, thus applying to a dielectric material that cannot be etched locally to an edge having a sharp slope.

公开(公告)号：JP2010045789A

公开(公告)日：2010-02-25

申请号：JP2009188027

申请日：2009-08-14

Applicant: St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー

Inventor： SIMONY LAURENT ,  VOGT LIONEL

IPC: H03M1/12 ,  H04N5/335

CPC classification number: H03M1/20 ,  H03M1/164 ,  H03M1/182 ,  H03M1/187 ,  H03M1/44 ,  H03M1/46 ,  H03M1/56

Abstract: PROBLEM TO BE SOLVED: To increase the number of bits of an analog-to-digital converter without excessively increasing complexity or processing time. SOLUTION: An analog-to-digital conversion method for converting an analog signal into n bits of digital data includes: a comparison step of comparing the amplitude of the analog signal with a threshold obtained by dividing full-scale analog signal amplitude by 2 k ((k) is an integer smaller than (n)); and a step of performing analog-to-digital conversion on the analog signal into n-k bits and obtaining the n-k most significant bits of the n bits of digital data when the result of the comparison step indicates that the amplitude of the analog signal is greater than the threshold, or obtaining the n-k least significant bits of the n bits of digital data when the result of the comparison step indicates that the amplitude of the analog signal is smaller than or equal to the threshold. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：增加模数转换器的位数，而不会过度增加复杂性或处理时间。 解决方案：一种用于将模拟信号转换成n位数字数据的模数转换方法包括：比较步骤，将模拟信号的幅度与通过将满量程模拟信号振幅除以 （（k）是小于（n）的整数）; 以及当所述比较步骤的结果表明所述模拟信号的幅度大于所述模拟信号的幅度时，对所述模拟信号执行模数转换为nk位并获得所述n位数字数据的nk个最高有效位的步骤 阈值，或者当比较步骤的结果指示模拟信号的幅度小于或等于阈值时，获得n位数字数据的nk个最低有效位。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008252105A

公开(公告)日：2008-10-16

申请号：JP2008118491

申请日：2008-04-30

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： BIANCHI RAUL ANDRES

IPC: H01L29/00 ,  G06F17/50 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC classification number: G06F17/5036

Abstract: PROBLEM TO BE SOLVED: To provide a transistor modeling to make the performance of a finally formed transistor to be close to that of simulated by the simulation model. SOLUTION: In a system for modeling an integrated circuit having at least an insulated gate field effect transistor, this system includes a generation means (MLB) for defining a parameter showing a mechanical stress applied to a transistor active region, and a processing means (MT) for determining at least a plurality of electrical parameter (P) for a transistor by considering the stress parameter. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供晶体管建模以使最终形成的晶体管的性能接近于由仿真模型模拟的晶体管的性能。 解决方案：在用于对至少具有绝缘栅场效应晶体管的集成电路进行建模的系统中，该系统包括用于定义表示施加到晶体管有源区的机械应力的参数的生成装置（MLB），以及处理 用于通过考虑应力参数来确定晶体管的至少多个电参数（P）的装置（MT）。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007243174A

公开(公告)日：2007-09-20

申请号：JP2007032606

申请日：2007-02-13

Applicant: St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー

Inventor： DUTARTRE DIDIER ,  LOUBET NICOLAS ,  TALBOT ALEXANDRE

IPC: H01L21/762 ,  H01L21/76 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a MOS transistor comprising a single crystal semiconductor film with no facets that is formed on a void portion, a laminated structure of single crystal thin films that prevents reduction in the device surface area, and a channel region that has a homogeneous thickness and is separated from an underlying semiconductor wafer by at least one non-single crystal layer with a homogeneous thickness.
SOLUTION: A method of forming a single crystal semiconductor film portion separated from a substrate comprises: a step of growing a single crystal semiconductor sacrifice film 38 and a single crystal semiconductor film 40 on a single crystal semiconductor active region in an insulation region 34 by selective epitaxial growth; a step of at least partially removing the raised insulation region 34; a step of removing the single crystal semiconductor sacrifice film 38 from the side, leaving a void; and a step of filling the void with an insulator, an electrical conductor, or a heat conductor.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种制造包括单晶半导体膜的MOS晶体管的方法，所述单晶半导体膜没有形成在空隙部分上的小面，单晶薄膜的层压结构防止器件表面积的降低 以及具有均匀厚度并且通过至少一个均匀厚度的非单晶层与下面的半导体晶片分离的沟道区域。 解决方案：形成从衬底分离的单晶半导体膜部分的方法包括：在绝缘区域的单晶半导体有源区上生长单晶半导体牺牲膜38和单晶半导体膜40的步骤 34通过选择性外延生长; 至少部分去除凸起绝缘区域34的步骤; 从侧面去除单晶半导体牺牲膜38留下空隙的步骤; 以及用绝缘体，电导体或导热体填充空隙的步骤。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006178464A

公开(公告)日：2006-07-06

申请号：JP2005367410

申请日：2005-12-21

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： BEZAL JEAN-RAPHAEL ,  PERMEZEL JEAN-MARIE ,  TROUSSEL GILLES

IPC: G09G3/28 ,  G09G3/20 ,  G09G3/288 ,  G09G3/293 ,  G09G3/296

CPC classification number: G09G3/296 ,  G09G3/293 ,  G09G2310/066 ,  G09G2330/06

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for controlling a plasma matrix screen in which a sharp drop of column potentials is suppressed. SOLUTION: The method for controlling the plasma matrix screen includes steps of; sequentially selecting rows of the matrix; and, for a selected row, deselecting a plurality of columns of the matrix which were previously selected during the selection of a previous row. To avoid excessive steepness of the falling sections of the column potentials, the previously selected two or more columns are non-simultaneously deselected. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种控制等离子体矩阵屏幕的方法和装置，其中抑制了列电位的急剧下降。 解决方案：用于控制等离子体矩阵屏幕的方法包括以下步骤： 依次选择矩阵的行; 并且对于所选择的行，取消选择在先前行的选择期间先前选择的矩阵的多个列。 为了避免柱电位的下降部分的过度陡峭度，先前选择的两个或更多个柱是非同时取消选择的。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005086822A

公开(公告)日：2005-03-31

申请号：JP2004258029

申请日：2004-09-06

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： CHIARUZZI EMMANUEL ,  ALADENISE DIDIER ,  VOS MARK ,  WALKER ALASTAIR ,  GILLET LYDIE ,  TERRAT MICHEL

IPC: G09G5/00 ,  G09G5/393 ,  H04N5/272 ,  H04N5/445

CPC classification number: H04N21/42653 ,  G09G5/393 ,  H04N5/272 ,  H04N5/44504 ,  H04N19/13 ,  H04N19/61 ,  H04N19/615 ,  H04N19/63 ,  H04N21/42692 ,  H04N21/4307 ,  H04N21/44008

Abstract: PROBLEM TO BE SOLVED: To provide a method to process video and graphic data that is not restricted in hardware and software. SOLUTION: The apparatus to process video and graphic data includes a component and a main random access memory capable of storing video and graphic data. The component includes a processing unit, a two-dimensional acceleration unit and an output interface. The two-dimensional acceleration unit synthesizes in real time an image including at least one video plane and at least one graphic plane and is capable of cooperating with the processing unit and the main memory to store the image in the main memory. The output interface extracts synthesized image data from the memory to send them to an image display means. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种处理在硬件和软件上不受限制的视频和图形数据的方法。 解决方案：处理视频和图形数据的装置包括能够存储视频和图形数据的组件和主随机存取存储器。 该组件包括处理单元，二维加速单元和输出接口。 二维加速单元实时地合成包括至少一个视频平面和至少一个图形平面的图像，并且能够与处理单元和主存储器协作以将图像存储在主存储器中。 输出接口从存储器中提取合成图像数据，将其发送到图像显示装置。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004343716A

公开(公告)日：2004-12-02

申请号：JP2004106933

申请日：2004-03-31

Applicant: St Microelectronics Sa ,  Stmicroelectronics Nv ,  エスティマイクロエレクトロニクス エスエー ,  エスティマイクロエレクトロニクス エヌヴィ

Inventor： BERENS FRIEDBERT ,  KREISELMAIER GERD

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/29 ,  H03M13/39 ,  H03M13/41 ,  H04L1/00

CPC classification number: H03M13/3905 ,  H03M13/2957 ,  H03M13/3738 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/4107 ,  H04L1/0046 ,  H04L1/0055 ,  H04L1/0059 ,  H04L1/0061 ,  H04L1/0066

Abstract: PROBLEM TO BE SOLVED: To provide a new methodology for blind detection of a transmission format of a convolution-encoded signal.
SOLUTION: The method for the blind detection of the transmission format of the convolution-encoded signal comprises the step of decoding the signal using a maximum a posteriori algorithm. Further the decoding step includes the steps of: decoding the signal by considering possible MF reference formats and delivering MF corresponding groups of soft output information; calculating from each group of soft output information a CRC (Cyclic Redundancy Check) word and comparing the calculated CRC word with the transmitted CRC word; selecting all the groups for which the calculated CRC word is equal to the transmitted CRC word; and selecting the actual transmission format of the encoded signal from at least one soft input information among the last pieces of the soft input information of each selected group.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004312727A

公开(公告)日：2004-11-04

申请号：JP2004099920

申请日：2004-03-30

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： BUSSON PIERRE ,  JOUFFRE PIERRE-OLIVIER ,  LOUIS-GAVET BERNARD

IPC: H04B1/26 ,  H04B1/16 ,  H04L27/148 ,  H04N7/20

CPC classification number: H04N7/20 ,  H04L27/148

Abstract: PROBLEM TO BE SOLVED: To provide a satellite digital television signal receiver which is completely integrated in a single chip.
SOLUTION: The electronic component composed of an integrated circuit mounted on the monolithic substrate comprises a direct sampling type tuning module which can receive a satellite digital television analog signal composed of several channels, and several channel decoding digital modules connected to an output part of a tuning module to simultaneously transmit several data packet streams corresponding to several different channels that is selected.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004228560A

公开(公告)日：2004-08-12

申请号：JP2003394079

申请日：2003-11-25

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： GROS JEAN MICKAEL ,  JOURDAN NICOLAS ,  MICHAILOS JEAN

IPC: C23C16/40 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

CPC classification number: C23C16/405 ,  H01L21/31604

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing tantalum pentoxide which is stable thermodynamically, has a good quality, and can be fabricated into an integrated circuit; and to provide a method for manufacturing a high-elastic dielectric which has a resistance to a mechanical stress and an excellent core-forming quality.
SOLUTION: A carrier material PL is heated at a heating temperature of 200°C to 400°C MCH, and a mixture of gases MG containing t-butyliminotris(diethylamino) tantalume(t-BuN=Ta(NEt
2 )
3 ) of a partial pressure more than 25 mTorr(3.3Pa) is circulated, being contacted with the heated carrier material in an atmosphere of oxidization.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003264242A

公开(公告)日：2003-09-19

申请号：JP2003000977

申请日：2003-01-07

Applicant: ST MICROELECTRONICS SA

Inventor： BIANCHI RAUL ANDRES

IPC: H01L29/00 ,  G06F17/50 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for modeling a transistor in which the true performance of a transistor fabricated finally can be approximated to a performance simulated using a simulation model. SOLUTION: A system for modeling an integrated circuit including at least one insulated gate field-effect transistor comprises a generator means (MLB) for defining parameter representating of mechanical stresses applied to the active area of the transistor, and a processing means (MT) for determining at least several electric parameters (P) of the transistor while taking account of the stress parameters. COPYRIGHT: (C)2003,JPO