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公开(公告)号：JP5306658B2
公开(公告)日：2013-10-02
申请号：JP2008002202
申请日：2008-01-09
Inventor： フ ウェンドン
CPC classification number: H04W72/085 , H04W16/14 , H04W72/082
Abstract: In order to satisfy the conflicting requirements for spectrum sensing and QoS of data transmission, it is highly desirable for a cognitive radio system, e.g. IEEE 802.22 WRAN, to perform spectrum sensing and data transmission simultaneously. Embodiments of the invention address critical issues of self-interference generated from a transmission unit to the co-located sensing unit when the simultaneous sensing and data transmission technique is applied. A number of interference mitigation techniques are described and analyses are given.
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102.发明专利
公开(公告)号：JP5265842B2
公开(公告)日：2013-08-14
申请号：JP2004106820
申请日：2004-03-31
Inventor： エム． チュウ アンソニー , キュー． ラオ トム
IPC: H01L23/12 , H01L23/00 , H01L23/13 , H01L23/29 , H01L23/31 , H01L23/34 , H01L23/36 , H01L23/367 , H01L23/433 , H01L23/498 , H05K3/34
CPC classification number: H01L23/562 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/3677 , H01L23/4334 , H01L23/49816 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/854 , H01L2924/00014 , H01L2924/01004 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H05K3/341 , H05K2203/1178 , H05K2203/304 , Y02P70/613 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00
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公开(公告)号：JP5059627B2
公开(公告)日：2012-10-24
申请号：JP2008002131
申请日：2008-01-09
Inventor： フ ウェンドン , エイ． ブランティス ジョージ , チュウ リウェン
CPC classification number: H04B1/715 , H04B1/7143 , H04B2001/7154 , H04W84/14
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104.发明专利
公开(公告)号：JP5043298B2
公开(公告)日：2012-10-10
申请号：JP2004340417
申请日：2004-11-25
Inventor： シー． マクアレキサンダー ジョセフ , エイ． ブランチャード リチャード
IPC: B81B3/00 , G01P15/135 , B81C1/00 , G01K5/62 , G01P15/18
CPC classification number: B81C1/00626 , B81B2201/0235 , B81B2203/0118 , B81B2203/033 , B81C2201/0109 , B81C2201/014
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公开(公告)号：JP5031139B2
公开(公告)日：2012-09-19
申请号：JP2000401113
申请日：2000-12-28
Inventor： プリート シン バンガ カンワル , チャウドゥリ バスカール , パラッツォーロ， ジュニア フランク , ザンピエリ ユーゴ
CPC classification number: G09G5/39 , G06F12/0875 , G09G2360/121 , G09G2360/122 , G09G2360/125 , G09G2360/128
Abstract: A system for accelerating graphics and a memory controller is used for controlling pixel data transmitted to and from the memory device. A cache memory is electrically coupled to the memory and is dynamically configurable to a selected usable size to exchange an amount of pixel data having the selected usable size with the memory controller. The memory device may be an SDRAM. The cache memory may also comprise a plurality of usable memory areas or tiles.
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Patent Agency Ranking106.发明专利
公开(公告)号：JP4908733B2
公开(公告)日：2012-04-04
申请号：JP2003280819
申请日：2003-07-28
Inventor： マイケル シーゲル ハリー
CPC classification number: H01L23/36 , H01L23/3121 , H01L23/4006 , H01L23/4093 , H01L2023/4043 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/83191 , H01L2224/83192 , H01L2924/1815
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107.发明专利
公开(公告)号：JP4820058B2
公开(公告)日：2011-11-24
申请号：JP2004013433
申请日：2004-01-21
Applicant: エスティーマイクロエレクトロニクス エス.アール.エル.STMicroelectronics S.r.l. , エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc
Inventor： マストマッテオ ウバルド , ロ プリオール ステファノ , パルミエリ ミシェル
CPC classification number: H01M8/241 , H01M4/8626 , H01M8/0247 , H01M8/1007 , Y02P70/56
Abstract: A microfuel cell includes a substrate and a plurality of spaced-apart PEM dividers extending outwardly to define anodic and cathodic microfluidic channels. An anodic catalyst/electrode lines at least a portion of the anodic microfluidic channels, and a cathodic catalyst/electrode lines at least a portion of the cathodic microfluidic channels. Each anodic and cathodic catalyst/electrode may extend beneath an adjacent portion of a PEM divider in some embodiments. Alternately, the microfuel cell may include a plurality of stacked substrates, in which a first substrate has first microfluidic fuel cell reactant channels. A PEM layer may be adjacent the first surface of the first substrate, an anodic catalyst/electrode layer may be adjacent one side of the PEM layer, and a cathodic catalyst/electrode layer may be adjacent an opposite side of the PEM layer. An adhesive layer may secure the first substrate to an adjacent substrate defining at least a second microfluidic fuel cell reactant channel.
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公开(公告)号：JP4669113B2
公开(公告)日：2011-04-13
申请号：JP2000301613
申请日：2000-10-02
Inventor： ハセガワ アツシ , エム． ジョーンズ アンドリュー , エイ． ケアリー ジョン
CPC classification number: H04L49/102 , G06F15/7825 , H04L49/555
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109.发明专利
公开(公告)号：JP4657617B2
公开(公告)日：2011-03-23
申请号：JP2004091404
申请日：2004-03-26
Inventor： エム． チュウ アンソニー , マイケル シーゲル ハリー
IPC: H01L23/473 , H01L23/34 , H01L23/367 , H01L23/433
CPC classification number: H01L23/473 , H01L23/3675 , H01L23/4334 , H01L2924/0002 , H01L2924/00
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110.发明专利
公开(公告)号：JP2010160895A
公开(公告)日：2010-07-22
申请号：JP2010029868
申请日：2010-02-15
Inventor： SLEZAK YARON , ZIKLIK ARYE , TRINH CUONG QUOC
IPC: G11C16/06 , G11C29/12 , G01R31/28 , G01R31/3185
CPC classification number: G01R31/318533
Abstract: PROBLEM TO BE SOLVED: To provide a memory chip of which the general purpose port can be used as a JTAG port.
SOLUTION: The memory chip which uses a multi-pin port as the JTAG port, is provided with a JTAG controller, at least one internal block, and composition unit, and one four-pins of the multi-pin port of the chip is selectively composed by the composition unit, and the JTAG data are transmitted to the JTAG controller or non-JTAG data are transmitted to at least one internal block. The composition unit can permanently or changeably composed in general. For example, the composition unit which can be changed, is a volatile memory (VM) composition unit or it can be product term output of programmable logic device (PLD).
COPYRIGHT: (C)2010,JPO&INPITAbstract translation: 要解决的问题：提供通用端口可以用作JTAG端口的存储器芯片。
解决方案：使用多针端口作为JTAG端口的存储器芯片设置有JTAG控制器，至少一个内部块和组合单元，以及多针端口的一个四针 芯片由组合单元选择性地组成，并且JTAG数据被发送到JTAG控制器，或者非JTAG数据被发送到至少一个内部块。 组合单元可以永久地或可变地组成。 例如，可以改变的组合单元是易失性存储器（VM）组成单元，或者它可以是可编程逻辑器件（PLD）的产品术语输出。 版权所有（C）2010，JPO＆INPIT
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