公开(公告)号：DE69130933D1

公开(公告)日：1999-04-08

申请号：DE69130933

申请日：1991-06-12

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： BITTING RICKY F

IPC: H03M1/14 ,  H03M1/38 ,  H03M1/46 ,  H03M1/68 ,  H03M1/76 ,  H03M1/80

公开(公告)号：MX9801173A

公开(公告)日：1998-11-29

申请号：MX9801173

申请日：1998-02-11

Applicant: SYMBIOS LOGIC INC

Inventor： DULAC KEITH BERNARD ,  FREEMAN PAUL MICHAEL

IPC: H04N5/93 ,  H04N7/173 ,  H04N21/472 ,  H04N07/173

Abstract: La invencion proporciona un aparato para manejar datos de vídeo y que incluye un dispositivo de almacenamiento (162) que contiene un vídeo para la reproduccion en un sistema de usuario (54) ubicado en una red de comunicaciones (56) y a una conexion de sistema (150) con un sistema de procesamiento de datos (100) y a una conexion de red (158) con la red de comunicaciones (56). El aparato incluye además un medio de transferencia para transferir el vídeo desde el dispositivo de almacenamiento (162) hacia la red (56) utilizando la conexion de red (158), en donde el vídeo se transfiere directamente desde el aparato hacia la red (56).

公开(公告)号：AU5521898A

公开(公告)日：1998-07-03

申请号：AU5521898

申请日：1997-12-10

Applicant: SYMBIOS LOGIC INC

Inventor： BRUNO KEVIN J

IPC: G06F13/40 ,  H03K19/0185 ,  H03K19/094

公开(公告)号：AU5249298A

公开(公告)日：1998-06-03

申请号：AU5249298

申请日：1997-11-10

Applicant: SYMBIOS LOGIC INC

Inventor： MCMANUS MICHAEL J

IPC: H03K19/003 ,  H03K19/0185

Abstract: The present invention is directed to a low-power input buffer comprising an inverter coupled to receive a first safe voltage range to a first node and coupled to provide an output signal, and a low-power circuit coupled to receive a second safe voltage range and coupled to control a voltage at the first node in response to the output signal and the second safe voltage range. The first and second safe voltage ranges preferably are equivalent. The low-power circuit includes series transistors coupled to the first node and responsive to the voltage at the output node. The low-power circuit further includes a transistor coupled between the first and second nodes and responsive to an input voltage. A method of operating an input buffer comprises the steps of pulling up a voltage of a first node in response to voltages of a second node and an output node and pulling down the voltage at the first node and the second node in response to an input voltage to provide low power consumption and a high impedance input.

公开(公告)号：DE69409422D1

公开(公告)日：1998-05-14

申请号：DE69409422

申请日：1994-02-25

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： DORAN DANIEL B

IPC: B08B7/04 ,  B08B7/00 ,  H01L21/00 ,  H01L21/304 ,  H01L21/673 ,  B08B3/08

Abstract: A system and a method for washing objects, such as cassettes and carriers used to hold and transport silicon wafers during manufacture of semiconductor chips. The method employs the steps of exposing the objects to ultraviolet radiation in a process chamber, spraying of developer fluid onto the objects, rinsing the objects, spraying of surfactant solution onto the objects, rinsing the objects and drying the objects using heated, filtered and ionized ultra low particle air (ULPA)

公开(公告)号：DE69405442T2

公开(公告)日：1998-04-02

申请号：DE69405442

申请日：1994-03-17

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： CRAFTS HAROLD S

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0175 ,  H03H7/38

Abstract: An I/O transceiver circuit, suitable for use on each integrated circuit of a multi-chip module, controls the output resistance of the transmitter portion (20). Control of the output resistance is achieved by a phase-locked-loop arrangement which includes a phase detector (102) a charge pump (106), a low-pass filter (108), a voltage controller (110) and a voltage controlled oscillator (120). Control of the output resistance allows operation without characteristically terminated I/O lines between multi-chip modules, thereby saving power otherwise wasted in the terminating resistors.

公开(公告)号：AU3350397A

公开(公告)日：1998-01-21

申请号：AU3350397

申请日：1997-06-27

Applicant: SYMBIOS LOGIC INC

IPC: G11B19/02 ,  G11B19/12 ,  G11B20/10 ,  G11B27/10 ,  G11B27/30 ,  G11B27/36

Abstract: The present invention includes a method of providing data to a memory device to be read at a first frequency comprising the steps of writing data to a memory device at a second frequency; blocking the writing of data after a predetermined amount of data is written; and writing data to the memory device in response to an address. Also included is a monitor circuit comprising a monitor state machine coupled to receive inputs including a comparison result, count signals and a load enable, and configured to output a data enable signal in response to the inputs.

公开(公告)号：AU3184697A

公开(公告)日：1998-01-14

申请号：AU3184697

申请日：1997-06-23

Applicant: SYMBIOS LOGIC INC

IPC: G05F3/26 ,  G05F1/46

Abstract: A bias current generator includes a first circuit component having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes an impedance element connected to the first circuit component and the second component, the impedance element (1) having an impedance which increases as an operating temperature of the impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current. Moreover, the bias current generator includes a mirroring circuit for generating a second current which mirrors the first current flowing through the impedance element. A method for generating a bias current that counteracts the effects temperature has upon electron and hole mobility is also disclosed.

公开(公告)号：DE69123100T2

公开(公告)日：1997-06-12

申请号：DE69123100

申请日：1991-08-21

Applicant: AT & T GLOBAL INF SOLUTION ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： CRAFTS HAROLD S ,  WALDRON ROBERT D

IPC: H03K3/356 ,  H03K3/3562

Abstract: A high speed CMOS clocked D-type flip-flop circuit (200) includes a master section (210) having input terminals (201, 203) adapted to receive D and D/ inputs and having parallel output terminals (247, 249) coupled to inputs of a slave section (220) which provides Q and Q/ outputs on Q and Q/ flip-flop output terminals (205, 207). The master and slave sections (210, 220) each include four CMOS tristate inverters (212-218; 222-228). The provision of parallel data paths having a small number of gates therein enables high-speed flip-flop operation to be achieved. A clock generating circuit (230) which may be selectively enabled generates true and complementary clock signals for the flip-flop circuit (200). In a modification, provision is made for a RESET signal to reset the flip-flop circuit (200).

公开(公告)号：DE69120901T2

公开(公告)日：1997-03-06

申请号：DE69120901

申请日：1991-10-25

Applicant: AT & T GLOBAL INF SOLUTION ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC FORT COLLINS

Inventor： DUKES GLENN E

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175