公开(公告)号：KR1020110119477A

公开(公告)日：2011-11-02

申请号：KR1020100039216

申请日：2010-04-27

Applicant: 삼성전자주식회사

Inventor： 정소영 ,  김정수 ,  오광철 ,  정재훈

IPC: G10L21/0208 ,  G10L21/028 ,  G11B20/24

Abstract: PURPOSE: A signal processing apparatus is provided to improve the quality of a purpose signal and to eliminate noise by revising voice using the ingredient of harmonic. CONSTITUTION: A noise canceling unit(102) eliminates noise form an input signal including a purpose signal and the noise. The noise canceling unit obtains the purpose signal. A first harmonic component is extracted from the purpose signal. A second harmonic component is extracted from the input signal. A purpose signal restoration unit(103) restores the purpose signal through calculated harmonics SNR(Signal to Noise Raito) based on the second harmonic component and the first harmonic component.

Abstract translation: 目的：提供一种信号处理设备，以提高目的信号的质量，并通过使用谐波成分修改语音来消除噪音。 构成：噪声消除单元（102）从包括目的信号和噪声的输入信号中消除噪声。 噪声消除单元获得目的信号。 从目的信号中提取一次谐波分量。 从输入信号中提取二次谐波分量。 目的信号恢复单元（103）通过基于二次谐波分量和一次谐波分量的计算出的谐波SNR（Signal to Noise Raito）恢复目的信号。

公开(公告)号：KR1020110047454A

公开(公告)日：2011-05-09

申请号：KR1020090104085

申请日：2009-10-30

Applicant: 한양대학교 산학협력단 ,  삼성전자주식회사

Inventor： 김태환 ,  손동익 ,  박원일 ,  정재훈 ,  심재호 ,  이정민

IPC: B82B3/00 ,  H01L29/40 ,  H01L31/0224

CPC classification number: H01L29/78684 ,  H01L51/0045 ,  H01L51/0529 ,  H01L51/0591

Abstract: PURPOSE: An electronic device and a method for manufacturing the same are provided to increase the capacitance of a memory device and reduce power consumption of the memory device using the superior conductivity of the grapheme thin film. CONSTITUTION: An electronic device(100) includes a substrate(10), a sandwich structure(50), and an electrode(55). The sandwich structure includes a grapheme thin film(30) between an upper insulting unit(40) and a lower insulating unit(20). The electrode is arranged on the sandwich structure. The electronic device further includes a lower electrode(15) between the substrate and the sandwich structure.

Abstract translation: 目的：提供一种电子设备及其制造方法，以增加存储器件的电容，并且使用该图形薄膜的优良导电性降低存储器件的功耗。 构成：电子设备（100）包括基板（10），夹层结构（50）和电极（55）。 夹层结构包括在上绝缘单元（40）和下绝缘单元（20）之间的图形薄膜（30）。 电极布置在夹层结构上。 电子设备还包括在基板和夹层结构之间的下电极（15）。

公开(公告)号：KR1020110020442A

公开(公告)日：2011-03-03

申请号：KR1020090078052

申请日：2009-08-24

Applicant: 한양대학교 산학협력단 ,  삼성전자주식회사

Inventor： 김태환 ,  정재훈 ,  손동익 ,  이정민 ,  양희연 ,  박원일

IPC: H01L21/60

CPC classification number: H01L51/441 ,  H01L51/0037 ,  H01L51/4233 ,  H01L51/428 ,  H01L2251/308 ,  Y02E10/549 ,  Y02P70/521 ,  Y10T156/10

Abstract: PURPOSE: An electronic device utilizing a graphene electrodes and an organic/inorganic hybrid composites and a method for manufacturing the same are provided to manufacture a electronic device more using an organic compound / inorganic material composite material simply with low costs. CONSTITUTION: In a electronic device utilizing a graphene electrodes and an organic/inorganic hybrid composites and a method for manufacturing the same, a bottom electrode(20) is formed on a substrate(10) for a device. A hole-transfer layer(30) is formed on the bottom electrode. A multiple layer(60) is formed on the hole-transport layer. A multiple layer is comprised of a polymer thin film(50) including nano particles(40). A top electrode(70) is formed between the multiple layers.

Abstract translation: 目的：提供一种利用石墨烯电极和有机/无机混合复合材料的电子器件及其制造方法，以简单的低成本更多地使用有机化合物/无机材料复合材料制造电子器件。 构成：在利用石墨烯电极和有机/无机混合复合材料的电子设备及其制造方法中，在用于器件的基板（10）上形成底部电极（20）。 在底部电极上形成空穴转移层（30）。 在空穴传输层上形成多层（60）。 多层由包括纳米颗粒（40）的聚合物薄膜（50）组成。 顶层电极（70）形成在多层之间。

公开(公告)号：KR1020100136785A

公开(公告)日：2010-12-29

申请号：KR1020090055073

申请日：2009-06-19

Applicant: 삼성전자주식회사

Inventor： 심선일 ,  허성회 ,  김기현 ,  김한수 ,  정재훈

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  H01L27/115

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427 ,  H01L27/0688 ,  H01L27/2436

Abstract: PURPOSE: A program method of a nonvolatile memory device is provided to reduce horizontal and vertical interference of a program by programming memory cells with multi bit data according to a shadow program method. CONSTITUTION: A 3D vertical channel array is formed on an intersection of bit lines(BL0-BLi-1) and string selection lines. The 3D vertical channel array includes strings with memory cells with multi-layered structure. A controller controls the program operation about the 3D vertical channel array. The memory cells are programmed to multi bit data according to a shadow program method. Each string is comprised of a string selection transistor(SST0), a ground selection transistor(GST0), and memory cells between the selection transistor and the ground selection transistor.

Abstract translation: 目的：提供一种非易失性存储器件的编程方法，用于通过根据阴影程序方法通过用多位数据编程存储器单元来减少程序的水平和垂直干扰。 构成：在位线（BL0-BLi-1）和串选择线的交点上形成3D垂直沟道阵列。 3D垂直通道阵列包括具有多层结构的存储单元的串。 控制器控制关于3D垂直通道阵列的程序操作。 根据阴影程序方法将存储单元编程为多位数据。 每个串由串选择晶体管（SST0），接地选择晶体管（GST0）以及选择晶体管和接地选择晶体管之间的存储单元构成。

公开(公告)号：KR1020100089022A

公开(公告)日：2010-08-11

申请号：KR1020100006475

申请日：2010-01-25

Applicant: 삼성전자주식회사

Inventor： 김두곤 ,  정재훈 ,  김한수 ,  조원석 ,  장재훈 ,  심선일

IPC: H01L27/115 ,  G11C16/00

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881 ,  H01L21/823425

Abstract: PURPOSE: The vertical structure of a non-volatile memory device is provided to reduce the length of the gate of ground-selection gate electrodes by forming two or more string-selection transistors. CONSTITUTION: A semiconductor pillar is vertically expanded to the upper side of a substrate. A NAND string(NS) is vertically expanded to the upper side of the substrate along the sidewall of the semiconductor pillar. The NAND string includes first selection transistors(TG1, TG2) which are adjacently arranged on one side of plurality of memory cells(MC). A plurality of word-lines(WL0 to WLn) is combined to a plurality of memory cells of the NAND string. A first selection line is commonly combined to the first selection transistors of the NAND string.

Abstract translation: 目的：提供非易失性存储器件的垂直结构，以通过形成两个或更多个串选择晶体管来减小接地选择栅电极的栅极的长度。 构成：半导体柱垂直扩展到基板的上侧。 NAND串（NS）沿着半导体柱的侧壁垂直扩展到衬底的上侧。 NAND串包括相邻地布置在多个存储单元（MC）的一侧上的第一选择晶体管（TG1，TG2）。 多个字线（WL0〜WLn）组合到NAND串的多个存储单元。 第一选择线通常组合到NAND串的第一选择晶体管。

公开(公告)号：KR1020100088829A

公开(公告)日：2010-08-11

申请号：KR1020090007945

申请日：2009-02-02

Applicant: 삼성전자주식회사

Inventor： 심선일 ,  김한수 ,  장재훈 ,  정재훈

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/11551 ,  G11C16/0483 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881 ,  H01L21/02579

Abstract: PURPOSE: A three dimensional memory device is provided to improve the reliability by reducing the malfunction of the device and the distribution of a current due to a resistance of a vertical channel structure and a common source line. CONSTITUTION: Vertical channel structures are arranged on a semiconductor substrate in a matrix shape. The vertical channel structures form a memory cell string(Ms). The memory cell string includes memory cells(Mmn), a ground selection transistor(GSTmna), and an auxiliary ground selection transistor(GSTmnb). The gates of the ground selection transistor and the auxiliary ground selection transistor are shared. The gates of the memory cells are expanded to a first direction in order to form word lines(WLn,1, WLn,2). A common source line(CSL) is formed between the vertical channel structures.

Abstract translation: 目的：提供三维存储器件，通过减少器件的故障和由于垂直沟道结构和公共源极线的电阻引起的电流分布来提高可靠性。 构成：垂直沟道结构以矩阵形状布置在半导体衬底上。 垂直通道结构形成存储单元串（Ms）。 存储单元串包括存储单元（Mmn），接地选择晶体管（GSTmna）和辅助地选择晶体管（GSTmnb）。 接地选择晶体管和辅助接地选择晶体管的栅极共享。 为了形成字线（WLn，1，WLn，2），存储单元的栅极扩展到第一方向。 在垂直通道结构之间形成公共源极线（CSL）。

公开(公告)号：KR100971552B1

公开(公告)日：2010-07-21

申请号：KR1020080069606

申请日：2008-07-17

Applicant: 삼성전자주식회사

Inventor： 장영철 ,  김한수 ,  정재훈 ,  정순문

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049

Abstract: 본 발명은 플래시 기억 장치 및 그 동작 방법을 제공한다. 이 장치는 하부 반도체층, 하부 반도체층에 형성된 하부 웰 영역, 및 하부 웰 영역 상에 형성된 복수의 하부 메모리 셀 유닛들을 포함하는 하부 메모리 셀 어레이, 하부 메모리 셀 에레이 상에 배치되고, 상부 반도체층, 상부 반도체층에 형성된 상부 웰 영역, 및 상부 웰 영역 상에 형성된 복수의 상부 메모리 셀 유닛들을 포함하는 상부 메모리 셀 어레이, 및 상부 메모리 셀 어레이 상에 배치되고 하부 웰 바이어스 라인 및 상부 웰 바이어스 라인을 포함하는 웰 바이러스 라인을 포함한다. 하부 웰 바이어스 라인은 하부 웰 영역과 전기적으로 접속하고, 상부 웰 바이어스 라인은 상부 웰 영역과 전기적으로 접속한다.
웰 스트래핑, 복층 구조, 바디 바이어스, 플래시 메모리

Abstract translation: 公开了闪存装置和操作方法。 闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。 底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。 顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。 井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到 顶好

公开(公告)号：KR1020100008960A

公开(公告)日：2010-01-27

申请号：KR1020080069606

申请日：2008-07-17

Applicant: 삼성전자주식회사

Inventor： 장영철 ,  김한수 ,  정재훈 ,  정순문

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049 ,  H01L21/823493 ,  H01L27/0688

Abstract: PURPOSE: A flash memory device including a 3D cell structure and an operation method thereof are provided to achieve high integration by independently performing erasure and program of lower and upper memory cells. CONSTITUTION: A lower memory cell array(10) comprises a lower semiconductor layer, a lower well domain formed on the lower semiconductor layer, and a plurality of lower memory cell units formed on the lower well domain. An upper memory cell array(20) is arranged on the lower memory cell array, and comprises an upper semiconductor layer, an upper well domain formed in the upper semiconductor layer, and a plurality of upper memory cell units formed on the upper well domain. A well bias line(32) comprising a lower well bias line and an upper well bias line is arranged on the upper memory cell array. The lower well bias line is electrically connected to the lower well domain and the upper well bias line is electrically connected to the upper well domain.

Abstract translation: 目的：提供一种包括3D单元结构及其操作方法的闪速存储器件，以通过独立执行上下存储单元的擦除和程序来实现高集成度。 构成：下部存储单元阵列（10）包括下半导体层，形成在下半导体层上的下阱区和形成在下阱结构域上的多个下存储单元单元。 上存储单元阵列（20）布置在下存储单元阵列上，并且包括上半导体层，形成在上半导体层中的上阱区和形成在上阱区上的多个上存储单元单元。 包括下阱偏置线和上阱偏置线的阱偏置线（32）布置在上存储单元阵列上。 下阱偏压线电连接到下阱区，上阱偏压线电连接到上阱结构域。

公开(公告)号：KR1020090056598A

公开(公告)日：2009-06-03

申请号：KR1020070123819

申请日：2007-11-30

Applicant: 삼성전자주식회사

Inventor： 김규홍 ,  오광철 ,  정재훈 ,  정소영

IPC: G10L21/0208 ,  G10L15/20 ,  H04R3/02 ,  H04R1/20

CPC classification number: H04R3/005 ,  G10L21/0208 ,  G10L2021/02166 ,  H04R2430/03 ,  H04R2430/20 ,  H04R2430/25

Abstract: A method and a device for removing noise from a sound signal inputted through a microphone are provided to minimize signal distortion generated in a low frequency band in a digital sound obtaining device, which is equipped with a small microphone array. A filter unit(210) filters a high frequency signal higher than a reference frequency and a lower frequency signal lower than the reference frequency from input signals obtained through a microphone array. A target high frequency signal generator(221) obtains a target high frequency signal by removing noise from the filtered high frequency signal. A target low frequency signal generator(222) obtains a target low frequency signal by removing the noise, which has a phase difference from a target signal, from the filtered low frequency signal. A signal composer(230) obtains a sound signal excluding the noise by composing the target high and low frequency signal.

Abstract translation: 提供一种用于从通过麦克风输入的声音信号中去除噪声的方法和装置，以最小化配备有小麦克风阵列的数字声音获取装置中的低频带中产生的信号失真。 滤波器单元（210）从通过麦克风阵列获得的输入信号中滤除高于基准频率的高频信号和低于基准频率的较低频率信号。 目标高频信号发生器（221）通过从滤波的高频信号中去除噪声来获得目标高频信号。 目标低频信号发生器（222）通过从经滤波的低频信号中去除与目标信号具有相位差的噪声来获得目标低频信号。 信号编辑器（230）通过组合目标高低频信号来获得不包括噪声的声音信号。

公开(公告)号：KR1020090037692A

公开(公告)日：2009-04-16

申请号：KR1020070103166

申请日：2007-10-12

Applicant: 삼성전자주식회사

Inventor： 정소영 ,  오광철 ,  정재훈 ,  김규홍

IPC: G10L21/0272 ,  H04R1/04 ,  G10L15/20

CPC classification number: H04R3/005

Abstract: A method and an apparatus for extracting a target sound signal from a mixed sound are provided to clearly separate a specific sound signal from the mixed sound including a plurality of sounds. A microphone array(210) obtains sound signals outputted from a plurality of sound sources in a mixed sound type. A beam forming unit(220) improves an amplitude by assigning proper weight to each received signal. The beam forming unit functions as a filter which spatially reduces noise. A phase difference between the signals inputted to each microphone and an array pattern. An emphasizing signal beam forming unit increases directivity sensitivity about a specific target sound source. A sound source signal is inputted to the microphone array. An adder adds signals in which difference is generated to the time of arrival.

Abstract translation: 提供一种用于从混合声音提取目标声音信号的方法和装置，用于将特定声音信号与包括多个声音的混合声音清楚地分离。 麦克风阵列（210）获得从混合声音类型的多个声源输出的声音信号。 波束形成单元（220）通过为每个接收到的信号分配适当的权重来提高振幅。 波束形成单元用作空间上降低噪声的滤波器。 输入到每个麦克风的信号与阵列图案之间的相位差。 强调信号光束形成单元增加关于特定目标声源的指向性灵敏度。 声源信号被输入到麦克风阵列。 加法器将产生差分的信号加到到达时间。