公开(公告)号：WO1997024763A1

公开(公告)日：1997-07-10

申请号：PCT/US1996020670

申请日：1996-12-27

Applicant: INTEL CORPORATION ,  HYDE, John, W. ,  SCHWARTZ, Abby, M. ,  BROWN, David, A.

Inventor： INTEL CORPORATION

IPC: H01L23/12

CPC classification number: H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/00

Abstract: An integrated circuit (IC) device package (101) that includes permanent identification (102) regarding the device characteristics, wherein the permanent identification (102) is at or below the surface of the package (101) and may indicate the operating frequency of an IC die within the package (101), as well as voltage requirement, etc.

Abstract translation: 一种集成电路（IC）器件封装（101），其包括关于器件特性的永久性识别（102），其中所述永久标识（102）在所述封装（101）的表面上或之下，并且可以指示所述器件特性的操作频率 封装（101）内的IC芯片以及电压要求等。

公开(公告)号：WO1997024678A1

公开(公告)日：1997-07-10

申请号：PCT/US1996020838

申请日：1996-12-27

Applicant: INTEL CORPORATION ,  HUANG, Chu-Yi ,  TSO, Michael, Man-hak

Inventor： INTEL CORPORATION

IPC: G06F13/42

CPC classification number: G06Q10/107 ,  Y10S707/99952

Abstract: A method and an apparatus for synchronization of a first set of mail with a second set of mail at the message/folder level (20). A memory (310) stores a mail synchronizer (340) for application independent e-mail message or folder in the mail boxes to be synchronized. An event log (344) is then generated for each mail box. The memory also has a synchronization mechanism (300) for making the first set of data and the second set of data equivalent by using the information in a Change List. A processor (316) runs the mail synchronizer (340).

Abstract translation: 一种用于在消息/文件夹级（20）处将第一组邮件与第二组邮件同步的方法和装置。 存储器（310）将用于应用程序的电子邮件消息或文件夹的邮件同步器（340）存储在要同步的邮箱中。 然后为每个邮箱生成事件日志（344）。 存储器还具有用于通过使用变更列表中的信息来产生第一组数据和第二组数据的同步机制（300）。 处理器（316）运行邮件同步器（340）。

公开(公告)号：WO1997023821A1

公开(公告)日：1997-07-03

申请号：PCT/US1996020603

申请日：1996-12-24

Applicant: INTEL CORPORATION ,  DULONG, Carole ,  MENNEMEIER, Larry, M. ,  PELEG, Alexander, D. ,  BUI, Tuan, H. ,  KOWASHI, Eiichi ,  MITTAL, Millind ,  EITAN, Benny ,  FISHER, Stephen, A. ,  MAYTAL, Benny

Inventor： INTEL CORPORATION

IPC: G06F07/38

CPC classification number: G06F9/30036 ,  G06F7/5443 ,  G06F9/30014 ,  G06F2207/3828

Abstract: A computer system (100) which includes a multimedia input device (121-129) which generates an audio or video input signal and a processor (109) coupled to the multimedia input device (121-129). The system further includes a storage device (107) coupled to the processor (109) and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor (109) to perform several steps. These steps include performing a packed multiply-add on a first set of values packed into a first source and a second set of values packed into a second source, each representing input signals to generate a packed intermediate result.

Abstract translation: 一种包括产生音频或视频输入信号的多媒体输入设备（121-129）和耦合到多媒体输入设备（121-129）的处理器（109）的计算机系统（100）。 该系统还包括耦合到处理器（109）并且其中存储有用于乘以和累加表示音频或视频输入信号的输入值的信号处理程序的存储设备（107）。 当由处理器执行时，信号处理程序使得处理器（109）执行几个步骤。 这些步骤包括对打包到第一源的第一组值和第二组值进行压缩乘法加法，该第二集合包含在第二源中，每一个代表输入信号以产生打包的中间结果。

公开(公告)号：WO1997023124A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020679

申请日：1996-12-19

Applicant: INTEL CORPORATION ,  LANGFORD, David

Inventor： INTEL CORPORATION

IPC: H05K09/00

CPC classification number: H05K9/0015

Abstract: A longitudinal electromagnetic emission sealer is constituted with an elongated elastomer core and a thin helical skin wrapped around the core. The elongated elastomer core is made of a flexible material that allows the core to be compressed in volume when pressure is exerted on the sealer. The helical skin is made of a material that can absorb electromagnetic emissions, even at minimal thickness, allowing the skin to wrap around the core in a helical manner easily. Additionally, a grove complementary in size to the sealer is provided to one side of the bracket of each card module for securing in place the sealer between the brackets of two card modules.

Abstract translation: 纵向电磁辐射密封器由细长的弹性体芯和缠绕在芯上的薄的螺旋状皮肤构成。 细长弹性体芯由柔性材料制成，当压力施加在密封剂上时，允许芯体积体积。 螺旋形皮肤由能够吸收电磁辐射的材料制成，即使在最小厚度下，也能容易地以螺旋方式缠绕在芯上。 此外，在每个卡模块的支架的一侧设置有与封口机尺寸互补的格子，用于将密封件固定在两个卡模块的支架之间。

公开(公告)号：WO1997023123A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020080

申请日：1996-12-18

Applicant: INTEL CORPORATION ,  BARROW, Michael

Inventor： INTEL CORPORATION

IPC: H05K07/02

CPC classification number: H05K3/0094 ,  B23K1/0016 ,  B23K11/11 ,  B23K2101/40 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K1/114 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K2201/0959 ,  H05K2201/10666 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/1178 ,  H05K2203/1394 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

Abstract: A ball grid array integrated circuit package (10) which has a plurality of vias (30) located within the solder pads (20) of a package substrate. The substrate supports an integrated circuit (24) which is connected to the solder pads (20) by the vias (30). Solder balls (36) used to solder the package (10) to an external printed circuit board (12) are attached to the solder pads (20) of the substrate. A solder mask plug (38) is formed within the vias (30) to prevent the solder balls (36) from wicking into the vias (30). Locating the vias (30) within the solder pads (20) optimizes the routing space of the substrate and increases the routing density of the package (10).

Abstract translation: 一种球栅阵列集成电路封装（10），其具有位于封装衬底的焊盘（20）内的多个通孔（30）。 衬底支撑通过通孔（30）连接到焊盘（20）的集成电路（24）。 用于将封装（10）焊接到外部印刷电路板（12）上的焊球（36）附接到基板的焊盘（20）。 在通孔（30）内形成有阻焊剂插塞（38），以防止焊球（36）吸入通孔（30）。 将焊盘（20）内的通路（30）定位可优化衬底的布线空间，并增加封装（10）的布线密度。

公开(公告)号：WO1997022989A1

公开(公告)日：1997-06-26

申请号：PCT/US1995016517

申请日：1995-12-18

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CRAFTS, Douglas, E. ,  MURALI, Venkatesan ,  LEE, Caroline, S.

IPC: H01L21/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/13023 ,  H01L2224/13116 ,  H01L2224/1357 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00014

Abstract: A method for removing Ball Limiting Metallurgy (BLM) layers (14, 15) from the surface of a wafer (10) in the presence of Pb/Sn solder bumps (17). In one embodiment, the BLM comprises two layers: titanium (14) and copper (15). After Pb/Sn solder-bumps (17) have been formed over the electrical contact pads (12) of the wafer (10), the BLM copper layer (15) is etched with a H2SO4+H2O2+H2O solution. While removing the copper layer (15), the H2SO4+H2O2+H2O etchant also reacts with the Pb/Sn solder bumps (17) to form a thin PbO protective layer (18) over the surface of the bumps (17). When the copper layer (15) has been etched away, the titanium layer (14) is etched with a CH3COOH+NH4F+H2O solution. The PbO layer (18) formed over the surface of the Pb/Sn solder bumps (17) remains insoluble when exposed to the CH3COOH+NH4F+H2O etchant, thereby preventing the solder bumps (17) from being etched in the presence of the CH3COOH+NH4F+H2O etchant. When the titanium etch is complete, the PbO layer (18) is removed from the surface of the Pb/Sn solder bumps (17) by exposing the bumps (17) to an HCl+NH2CSNH2+NH4Cl+H2O solution.

Abstract translation: 一种在Pb / Sn焊锡凸块（17）的存在下从晶片（10）的表面去除球限制冶金（BLM）层（14,15）的方法。 在一个实施例中，BLM包括两层：钛（14）和铜（15）。 在晶片（10）的电接触焊盘（12）上形成Pb / Sn焊料凸起（17）之后，用H 2 SO 4 + H 2 O 2 + H 2 O溶液蚀刻BLM铜层（15）。 在去除铜层（15）时，H2SO4 + H2O2 + H2O蚀刻剂也与Pb / Sn焊料凸点（17）反应，在凸块（17）的表面上形成薄的PbO保护层（18）。 当蚀刻铜层（15）时，用CH 3 COOH + NH 4 F + H 2 O溶液蚀刻钛层（14）。 当暴露于CH3COOH + NH4F + H2O蚀刻剂时，形成在Pb / Sn焊料凸块（17）表面上的PbO层（18）保持不溶，从而防止在CH3COOH存在下蚀刻焊料凸点（17） + NH4F + H2O蚀刻剂。 当钛蚀刻完成时，通过将凸块（17）暴露于HCl + NH 2 CSNH 2 + NH 4 Cl + H 2 O溶液，从Pb / Sn焊料凸块（17）的表面去除PbO层（18）。

公开(公告)号：WO1997018669A1

公开(公告)日：1997-05-22

申请号：PCT/US1996017929

申请日：1996-11-12

Applicant: INTEL CORPORATION ,  BATCHELOR, Steve

Inventor： INTEL CORPORATION

IPC: H04N05/445

CPC classification number: H04N7/088 ,  H04N5/445 ,  H04N7/0887 ,  H04N9/641

Abstract: A system that displays text and graphic information with broadcasted television images includes a VBI inserter (16) for inserting data into the VBI of a publicly broadcasted video signal. An associated personal computer (10) includes a VBI decoder for separating the data from the video signal. The separated data contains command and address information which instruct the PC to retrieve text/graphic information from a storage device, and display the information on a monitor (30). The broadcaster inserts data that retrieves text and graphic information which correspond to the television image displayed by the monitor. The retrieved text and graphic data may be stored for later viewing by the user.

Abstract translation: 显示具有广播电视图像的文本和图形信息的系统包括用于将数据插入到公开广播的视频信号的VBI中的VBI插入器（16）。 相关联的个人计算机（10）包括用于从视频信号分离数据的VBI解码器。 分离的数据包含指示PC从存储装置检索文本/图形信息的命令和地址信息，并将该信息显示在监视器（30）上。 广播公司插入检索与显示器显示的电视图像相对应的文本和图形信息的数据。 检索的文本和图形数据可以被存储以供用户稍后观看。

公开(公告)号：WO1997018602A1

公开(公告)日：1997-05-22

申请号：PCT/US1996018176

申请日：1996-11-13

Applicant: INTEL CORPORATION ,  BABCOCK, Sean, R.

Inventor： INTEL CORPORATION

IPC: H01R09/09

CPC classification number: G06F13/409

Abstract: A dual-in-line Universal Serial Bus connector (345) including a plurality of Universal Serial Bus ports (400, 405) oriented adjacent to each other in a longitudinal direction. The dual-in-line Universal Serial Bus connector further includes a plurality of signal pins (435), coupled to the plurality of Universal Serial Bus ports (400, 405), which are configured to receive data input into at least one of the plurality of Universal Serial Bus ports (400, 405) and a pair of mounting tabs (430a, 430b). The positioning of the mounting tabs (430a, 430b) and signal pins (435) enable this connector to be used as a substitute for one of the serial COM port connectors (350) normally used by the computer system.

Abstract translation: 一种双列直插通用串行总线连接器（345），其包括在纵向方向上彼此相邻定向的多个通用串行总线端口（400,405）。 双列直插通用串行总线连接器还包括耦合到多个通用串行总线端口（400,405）的多个信号引脚（435），其被配置为接收输入到多个 的通用串行总线端口（400,405）和一对安装接头（430a，430b）。 安装突片（430a，430b）和信号引脚（435）的定位使得该连接器能够用作计算机系统通常使用的串行COM端口连接器（350）之一。

公开(公告)号：WO1997014175A2

公开(公告)日：1997-04-17

申请号：PCT/US1996015281

申请日：1996-09-23

Applicant: INTEL CORPORATION ,  MOON, Peter, K. ,  LANDAU, Berni, W. ,  KRICK, David, T.

Inventor： INTEL CORPORATION

IPC: H01L00/00

CPC classification number: H01L21/76235 ,  H01L21/76221 ,  H01L21/76232 ,  Y10S148/05

Abstract: A method of forming a trench isolation region. The method of the present invention comprises the steps of forming an opening in a semiconductor substrate, oxidizing the opening a first time, and then etching the oxidized opening with a wet etchant comprising HF. The opening is then oxidized a second time.

Abstract translation: 一种形成沟槽隔离区域的方法。 本发明的方法包括以下步骤：在半导体衬底中形成开口，第一次氧化开口，然后用包含HF的湿蚀刻剂蚀刻氧化开口。 然后开口第二次被氧化。

公开(公告)号：WO1997011418A2

公开(公告)日：1997-03-27

申请号：PCT/US1996011716

申请日：1996-07-15

Applicant: INTEL CORPORATION ,  AJANOVIC, Jasmin ,  MURDOCH, Robert, N. ,  DOBBINS, Timothy, M. ,  SREENIVAS, Aditya ,  SAILER, Stuart, E. ,  RABE, Jeffrey, L.

Inventor： INTEL CORPORATION

IPC: G06F00/00

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

Abstract translation: 公开了一种用于调节由计算机系统中的处理器在总线上发布的交易的延迟的方法和装置。 总线事务记录器耦合到总线上，处理在总线上发出的事务的编码信号。 当总线上发出待处理的事务请求时，耦合到总线的线路发送指示信号。 当新的待处理事务在总线上等待时，CPU等待时间计时器会重新计算总线上的当前事务。 当等待时间超过预定时间时，CPU等待时间会输出到期信号。 交易处理器单元耦合到总线事务记录器，线路和CPU等待时间计时器。 交易处理器单元在事务处理器接收到指示等待发送在总线上的待处理事务的指示信号时，在总线上发出的交易的编码信号指示发出的交易 总线是延迟的候选者，当CPU等待时间输出到期信号时。