公开(公告)号：US20180293011A1

公开(公告)日：2018-10-11

申请号：US15482971

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Prasoonkumar Surti ,  Aravindh V. Anantaraman ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu

IPC: G06F3/06 ,  G06F1/32 ,  G11C11/406

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a memory comprising one or more physical memory chips, and a processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips. The working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set.

公开(公告)号：US20180268597A1

公开(公告)日：2018-09-20

申请号：US15988157

申请日：2018-05-24

Applicant: Intel Corporation

Inventor： Bimal Poddar ,  Prasoonkumar Surti ,  Rahul P. Sathe

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/60 ,  G06T15/04 ,  G06T19/20

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/04 ,  G06T15/506 ,  G06T19/20 ,  G06T2200/04 ,  G06T2200/28 ,  G06T2210/62

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

公开(公告)号：US09053040B2

公开(公告)日：2015-06-09

申请号：US14471106

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti

IPC: G09G5/36 ,  G06T1/60 ,  G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/401 ,  G06F2212/455 ,  G06T1/60 ,  G06T2200/28 ,  G09G5/36 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/122

Abstract: Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may be checked to see whether both a subspan request hits an unlit bit and a modify message was already sent. If so, the modification message may be filtered.

Abstract translation: 可以对修改消息进行过滤，以减少渲染缓存和帧缓冲区压缩之间的消息通道的负载。 可以检查一组高速缓存行，以查看子跨越请求是否触发不亮位，并且已经发送修改消息。 如果是这样，可以对修改消息进行过滤。

公开(公告)号：US12293430B2

公开(公告)日：2025-05-06

申请号：US17356043

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Jay Jardosh ,  Prasoonkumar Surti ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60

Abstract: Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource, calculate a memory address for each pixel associated with the typed UAV message, and collect a plurality of fragments from processed typed UAV messages.

公开(公告)号：US12243155B2

公开(公告)日：2025-03-04

申请号：US17357423

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Ronald Silvas ,  Karol A. Szerszen

IPC: G06T15/50 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/04 ,  G06T15/80

Abstract: Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.

公开(公告)号：US12229867B2

公开(公告)日：2025-02-18

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike MacPherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T17/20 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/40

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

公开(公告)号：US20250037359A1

公开(公告)日：2025-01-30

申请号：US18793166

申请日：2024-08-02

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T15/50 ,  G06T1/60 ,  G06T11/20 ,  G06T11/40 ,  G06T15/80

Abstract: Systems, apparatuses and methods may provide for technology that selects an anti-aliasing mode for a vertex of a primitive based on a parameter associated with the vertex and generates a coverage mask based on the selected anti-aliasing mode. Additionally, one or more pixels corresponding to the vertex may be shaded based at least partly on the coverage mask, wherein the selected anti-aliasing mode varies across a plurality of vertices in the primitive.

公开(公告)号：US12198221B2

公开(公告)日：2025-01-14

申请号：US18436494

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US20240394956A1

公开(公告)日：2024-11-28

申请号：US18675746

申请日：2024-05-28

Applicant: Intel Corporation

Inventor： Sven Woop ,  Michael J. Doyle ,  Sreenivas Kothandaraman ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Carsten Benthin ,  Prasoonkumar Surti ,  Holger Gruen ,  Stephen Junkins ,  Adam Lake ,  Bret G. Alfieri ,  Gabor Liktor ,  Joshua Barczak ,  Won-Jong Lee

IPC: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

公开(公告)号：US20240355032A1

公开(公告)日：2024-10-24

申请号：US18436688

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Atsuo Kuwahara ,  Deepak S. Vembar ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Prasoonkumar Surti ,  Murali Ramadoss

IPC: G06T15/00 ,  G06F9/50 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

CPC classification number: G06T15/005 ,  G06F9/5027 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T2215/16

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.