公开(公告)号：US20200294180A1

公开(公告)日：2020-09-17

申请号：US16355303

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Josh Mastronarde ,  Naveen Matam ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：US20190012762A1

公开(公告)日：2019-01-10

申请号：US16039509

申请日：2018-07-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Akif Ali

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80 ,  G06F15/08 ,  G06T11/00 ,  G06T1/60 ,  H04L12/933

CPC classification number: G06T1/20 ,  G06F15/08 ,  G06T1/60 ,  G06T11/001 ,  G06T15/005 ,  G06T15/80 ,  H04L49/109

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

公开(公告)号：US10102604B2

公开(公告)日：2018-10-16

申请号：US15083689

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Akif Ali

IPC: G06F15/16 ,  G06T1/20 ,  G06T1/60 ,  G06F15/08 ,  G06T11/00 ,  G06T15/00 ,  G06T15/80 ,  H04L12/933

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.