公开(公告)号：JPH06124945A

公开(公告)日：1994-05-06

申请号：JP27468292

申请日：1992-10-13

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/90

Abstract: PURPOSE:To eliminate steps in an insulating film so that no complication of processes accompanying an increase in the number wiring layers may be caused. CONSTITUTION:An insulating film 4 is newly deposited separately on an insulating film by using a semiconductor substrate 1 where an insulating film 3 provided with a buried conductor for electric contact in a contact position. Then, after selective etching of a part of the wiring formation region in the other insulating film down to the depth reaching the buried conduction part while depositing a metal film for wiring to the thickness where an etching removal part 5 is completely buried, etching is performed until the surface of the other insulating film is exposed to the metal film so as to form the wiring.

公开(公告)号：JPH0574732A

公开(公告)日：1993-03-26

申请号：JP23434191

申请日：1991-09-13

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/28 ,  H01L21/306

Abstract: PURPOSE:To provide a formation method of a contact hole having the least dispersion in the hole sectional shape capable of properly corresponding to various individual hole sectional shapes. CONSTITUTION:A semiconductor substrate 1 provided with an insulating film 2 on the surface thereof and a mask 3 having windows 3a in the contact hole formation positions on the insulating film 2 is prepared. In order to make the contact holes in this semiconductor substrate 1, this insulating film 2 is laminated of two oxide films 2a, 2b in different etching rates so that the oxide film 2a of lower etching rate may be located in the lower side (nearer to the substrate 1) to be anisotropically or isotropically etched away. Through these procedures, the through-holes piercing both oxide films 2b, 2a making the hole diameter of the upper oxide film layer 2b wider than that of the lower side film layer 2a are to be made as the contact holes.

公开(公告)号：JPH02219235A

公开(公告)日：1990-08-31

申请号：JP4098889

申请日：1989-02-20

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA ,  SAIJO TAKASHI

IPC: H01L21/336 ,  H01L29/78

Abstract: PURPOSE:To obtain a field effect semiconductor device free of irregularity of impurity concentration and region length by a method wherein, after a polysilicon layer surface is oxidized for a semiconductor substrate and then the oxidized part is eliminated, impurity is supplied. CONSTITUTION:A semiconductor substrate 1 to which impurity for forming a drain region 5 and a source region 6 is supplied is used] said substrate 1 is subjected to treatment for oxidizing the surface of a polysilicon layer 3. After an oxidized part 3a of the polysilicon layer surface is eliminated, a small amount of impurity is supplied, thereby forming a low concentration impurity region 5a for LDD (lightly doped drain) structure on the end of the drain region 5. In this case, the impurity concentration of the low concentration impurity region is determined only by the impurity amount supplied to the substrate surface. For example, it is easy to supply impurity to the substrate surface by ion implantation so as to exactly obtain a specified amount. Thereby, the irregularity of impurity concentration in the low concentration region can be reduced, and the irregularity of region length also is reduced.

公开(公告)号：JPH01225332A

公开(公告)日：1989-09-08

申请号：JP5234688

申请日：1988-03-04

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/76

Abstract: PURPOSE:To prevent an impurity for channel stopper from being implanted under a nitride film even when a photoresist film is displaced from a mask by using the mask which has been formed by laying an oxide film between two- or more-layer nitride films. CONSTITUTION:A nitride layer is deposited on an SiO2 film 2; by heat-treating its surface, it is oxidized and transformed into an SiO2 film; an oxide film 2' and a nitride film 3 are formed. Then, a nitride film 3' is formed on the oxide film 2; a photoresist film 4 covering a MOSFET formation region is formed on this four-layer structure. A part not covered with said photoresist film 4 out of three films 2', 3, 3' is etched and removed; the photoresist film 4 is removed; a mask is formed; after that, a P-type impurity for channel stop per use is ion-implanted. Since the mask is thick, the impurity does not reach a semiconductor substrate under the mask. Even when a C-MOS is to be formed, the impurity does not reach the semiconductor substrate under the mask; even when a resist layer covering a well is displaced, thus no problem is caused.

公开(公告)号：JPS63194353A

公开(公告)日：1988-08-11

申请号：JP2675087

申请日：1987-02-06

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/092

Abstract: PURPOSE:To inhibit the formation of a parasitic channel, and to prevent the lowering of element characteristics due to leakage currents flowing between channels by selectively growing a thick oxide film for reducing currents flowing between the p channel section and the n channel section to the bottom of a trench. CONSTITUTION:A well 2 as a p-type conductive region is formed to the surface of a semiconductor substrate 1. A first buried layer 12, a second buried layer 13 and a channel stopper region 14 are shaped. A first epitaxial layer 15 and a second epitaxial layer 17 are grown onto the layers 12, 13 and the region 14, and a trench 9 is formed. Side walls consisting of a second nitride film 24 are shaped onto the side walls of the trench 9, and thick oxide films 25 as field oxide films are formed, using first nitride films 21 as masks. P-type diffusion layers 26 and n-type diffusion layers 27 are shaped, and brought into contact with the buried layers 12, 13. A polycrystalline Si layer 3 for a gate oxide-film 30 gate electrode is formed, and a p-type diffusion layer 28 and an n-type diffusion layer 29 are shaped. Contact holes for wirings are formed, and aluminum wirings 32 are shaped.

公开(公告)号：JPS62172722A

公开(公告)日：1987-07-29

申请号：JP1498686

申请日：1986-01-27

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/3205 ,  H01L21/28

Abstract: PURPOSE:To lessen the amount of side etching to a CVD oxide film and an Si thermal oxide film by a method wherein, at a point the formation of an opening ends by etching the CVD oxide film, a sidewall is formed in the opening part by heat-treating a photo resist and an etching is performed on the Si thermal oxide film. CONSTITUTION:A pattern is formed on a CVD oxide film 3 using a P-type photo resist 5 as a mask and an etching is performed on two layers of an Si thermal oxide film 2 and the CVD oxide film 3. The etching proceeds from the part of the CVD oxide film 3, the CVD oxide film 3 only is opened and the thermal oxide film 2 is exposed. Then, if an Si substrate 1 is heated at 180 deg.C for 30min or thereabouts, the photo resist 5 is softened and a sidewall 12 is formed on the inner periphery of the opening part. Then, if an etching is performed on the Si thermal oxide film 2, a contact hole 9 can be formed. Then, the photo resist 5 is removed and an Al wiring 11 is formed through the contact hole 9. Thereby, perforating of the contact hole of the oxide film formed by superposing the CVD oxide film on the Si thermal oxide film can be performed as the pattern is formed.

公开(公告)号：JPS58211856A

公开(公告)日：1983-12-09

申请号：JP9463082

申请日：1982-05-31

Applicant: Matsushita Electric Works Ltd

Inventor： OKA NAOMASA

IPC: B24B9/06 ,  B24B37/04 ,  B24B37/10 ,  B24B37/30 ,  H01L21/304

CPC classification number: H01L21/0201 ,  B24B9/065

Abstract: PURPOSE:To have quick and accurate grinding of a silicon wafer for the purpose of determination of its dispersion layer, by performing the grinding while the wafer is vacuum attracted and the position to be ground is protruded from a slit in the grinding guide plate which is inclined to a specific grinding angle. CONSTITUTION:The part of wafer 13 to be measured is cut off, and the wafer 13a after cutting is set on the slit part 12 and vacuum attracted to a attraction surface 10 of a vacuum attraction means 7. Then an end of the wafer 13a is allowed to hop up from the slit 12. This protruding part is coated with a small amount of abrasive material and ground by rotating the grinding jig 9 while the wafer is slide on the grinding guide plate 8. Because this grinding guide plate 8 is inclined at a specific grinding angle theta to the attraction surface 10, the wafer 13a can be ground at this specific angle. After grinding, the abrasive material attached to the wafer 13a is removed, and the P layer is colored by staining to serve for observation by microscope, in which the depth of the dispersion layer in the wafer 13 is calculated.

Abstract translation: 目的：为了快速准确地研磨硅晶片以确定其分散层，通过在晶片被真空吸引时进行研磨，并且被研磨的位置从研磨导向板中的狭缝突出 倾向于特定的研磨角度。 构成：切断待测量的晶片13的部分，将切割后的晶片13a设定在狭缝部12上，将真空吸附到真空吸引装置7的吸附面10.然后，晶片13a的端部 允许从狭缝12上升。该突出部分涂覆有少量研磨材料，并且通过在晶片在研磨引导板8上滑动的同时旋转研磨夹具9而研磨。由于该研磨引导板8倾斜 相对于吸引表面10的特定研磨角度θ，晶片13a可以以该特定角度被研磨。 研磨后，除去附着在晶片13a上的研磨材料，通过染色使P层着色，以便计算出晶片13中的分散层的深度，通过显微镜进行观察。