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    METHOD OF FABRICATING MOS DEVICE
    101.
    发明申请
    METHOD OF FABRICATING MOS DEVICE 有权
    制造MOS器件的方法

    公开(公告)号：US20150017777A1

    公开(公告)日：2015-01-15

    申请号：US13940103

    申请日：2013-07-11

    Applicant: United Microelectronics Corp.

    Inventor： Tsung-Hung Chang ,  Yi-Wei Chen ,  I-Fang Huang

    IPC: H01L29/66

    CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

    Abstract: Provided is a method of fabricating a MOS device including the following steps. A gate structure is formed on a substrate and a first spacer is formed at a sidewall of the gate structure. A first implant process is performed to form source and drain extension regions in the substrate. A spacer material layer is formed on the gate structure, the first spacer and the substrate. A treatment process is performed so that stress form the spacer material layer is applied onto and memorized in a channel between two source and drain extension regions. An anisotropic process is performed to remove a portion of the spacer material so that a second spacer is formed. A second implant process is performed to form source and drain regions in the substrate.

    Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 栅极结构形成在衬底上，并且第一间隔物形成在栅极结构的侧壁处。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域。 在栅极结构，第一间隔物和衬底上形成间隔物层。 执行处理过程，使得形成间隔物材料层的应力被施加到并存储在两个源极和漏极延伸区域之间的沟道中。 执行各向异性处理以去除间隔物材料的一部分，从而形成第二间隔物。 执行第二注入工艺以在衬底中形成源区和漏区。

    ELECTRICAL CONTACT
    102.
    发明申请
    ELECTRICAL CONTACT 审中-公开
    电气联系

    公开(公告)号：US20140225262A1

    公开(公告)日：2014-08-14

    申请号：US14261409

    申请日：2014-04-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： I-Ming Tseng ,  Tsung-Lung Tsai ,  Yi-Wei Chen

    IPC: H01L23/498

    CPC classification number: H01L23/49866 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrical contact includes a substrate, at least an insulation layer, a metal layer, a conductive layer, and a metal silicide layer. The substrate includes at least a silicon region. The insulation layer is disposed on the substrate and includes at least a contact hole exposing the silicon region. The metal layer is formed on the sidewalls and the bottom of the contact hole. The metal layer adjacent to the bottom surface is thinner than the metal layer on the sidewalls. The conductive layer covers the metal layer and fills up the contact hole. The metal silicide layer is adjacent to the bottom of the contact hole.

    Abstract translation: 电接触包括至少绝缘层，金属层，导电层和金属硅化物层的衬底。 衬底至少包括硅区域。 绝缘层设置在基板上，并且至少包括露出硅区域的接触孔。 金属层形成在接触孔的侧壁和底部上。 与底面相邻的金属层比侧壁上的金属层薄。 导电层覆盖金属层并填充接触孔。 金属硅化物层与接触孔的底部相邻。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    103.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140191298A1

    公开(公告)日：2014-07-10

    申请号：US13737949

    申请日：2013-01-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Wei Chen ,  Chien-Chung Huang ,  Kok Seen Lew

    IPC: H01L29/40 ,  H01L29/45

    CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.

    Abstract translation: 半导体器件包括半导体衬底，金属栅极结构，至少外延层，层间电介质，至少接触孔，至少金属硅化物层和含氟层。 半导体衬底至少具有栅极区域和至少与栅极区域相邻的源极/漏极区域。 栅极结构设置在栅极区域内的半导体衬底上。 外延层设置在源极/漏极区域内的半导体衬底上。 层间电介质覆盖半导体衬底，栅极结构和外延层。 接触孔穿透层间电介质到达外延层。 金属硅化物层形成在外延层中并且位于接触孔的底部。 含氟层设置在外延层中或外延层中并且在金属硅化物层的侧面附近。

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