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    System with wide operand architecture and method
    117.
    发明公开
    System with wide operand architecture and method 有权
    Prozessor und Verfahren zurDurchführungeines Breitschaltungsbefehls mit breitem操作数

    公开(公告)号：EP2309383A1

    公开(公告)日：2011-04-13

    申请号：EP10179608.4

    申请日：1999-08-24

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： Hansen, Craig

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318

    CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/4991 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3885

    Abstract: A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).

    Abstract translation: 具有访问单元的四个副本的通用处理器，具有访问指令获取队列A队列（101-104）。 每个A队列（101-104）耦合到耦合到两个访问功能单元A（109-116）的访问寄存器文件AR（105-108）。 在典型的实施例中，处理器的每个线程可以具有六十四个通用寄存器的数量级。 访问单元通过四个同时执行的线程独立地起作用，并且通过执行加载和存储指令来执行算术和分支指令以及访问存储器来进行每个计算控制流程。 这些访问单元还提供广泛的操作数说明。 这八个访问功能单元A（109-116）产生访问寄存器文件（105-108）和存储器地址到共享存储器系统（117-120）的结果。

    System for matrix multipy operation with wide operand architecture and method
    118.
    发明公开
    System for matrix multipy operation with wide operand architecture and method 有权
    Prozessor und Verfahren zur Matrixmultiplikation mit einem breiten Operand

    公开(公告)号：EP2302510A1

    公开(公告)日：2011-03-30

    申请号：EP10179598.7

    申请日：1999-08-24

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： Hansen, Craig

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318

    CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/4991 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3885

    Abstract: A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).

    Abstract translation: 具有访问单元的四个副本的通用处理器，具有访问指令获取队列A队列（101-104）。 每个A队列（101-104）耦合到耦合到两个访问功能单元A（109-116）的访问寄存器文件AR（105-108）。 在典型的实施例中，处理器的每个线程可以具有六十四个通用寄存器的数量级。 访问单元通过四个同时执行的线程独立地起作用，并且通过执行加载和存储指令来执行算术和分支指令以及访问存储器来进行每个计算控制流程。 这些访问单元还提供广泛的操作数说明。 这八个访问功能单元A（109-116）产生访问寄存器文件（105-108）和存储器地址到共享存储器系统（117-120）的结果。

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