公开(公告)号：EP1591949A3

公开(公告)日：2008-06-18

申请号：EP05252083.0

申请日：2005-04-01

Applicant: Renesas Technology Corp.

Inventor： Nishizawa, Hirotaka, c/o Renesas Technology Corp. ,  Osawa, Kenji, c/o Renesas Technology Corp. ,  Osako, Junichiro, c/o Renesas Technology Corp. ,  Wado, Tamaki, c/o Renesas Technology Corp. ,  Sugiyama, Michiaki, c/o Renesas Technology Corp. ,  Totsuka, Takashi, c/o Renesas Technology Corp.

IPC: G06K19/07

CPC classification number: G06K19/077 ,  G06K7/0021 ,  G06K13/06 ,  G06K19/07732 ,  G06K19/07741 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  Y10S439/948 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: This invention is to provide an ultra-miniaturized, thin-sized memory card provided with a mechanism for preventing a wrong insertion to a memory card slot. Amulti-functionmemory card is composed of a card body and a cap for housing the card body. The card body is made of mold resin that encapsulates plural semiconductor chips mounted on a main surface of a wiring substrate. The card body is housed into the cap with the back face of the wiring substrate facing outward. Guide channels are provided at both side faces of the cap for preventing that the card is inserted upside down. Further, a convex section is provided at the trailing edge of the cap for preventing that the card is inserted in the wrong direction.

公开(公告)号：EP1916813A3

公开(公告)日：2008-05-07

申请号：EP07119414.6

申请日：2007-10-26

Applicant: FUJITSU TEN LIMITED ,  FUJITSU LIMITED ,  Renesas Technology Corp.

Inventor： Noumi, Kaoru, c/o FUJITSU TEN LIMITED ,  Nishihashi, Susumu, c/o FUJITSU TEN LIMITED ,  Katou, Tomoyuki, c/o FUJITSU TEN LIMITED ,  Ishikawa, Yukio, c/o FUJITSU TEN LIMITED ,  Umezaki, Yasuyuki, c/o Fujitsu Limited ,  Ebeshu, Hidetaka, c/o Fujitsu Limited ,  Koide, Shigeo, c/o Fujitsu Limited ,  Fujisawa, Yukio, c/o Renesas Technology Corp. ,  Shimauchi, Hiroaki, c/o Renesas Technology Corp.

IPC: H04L12/66

CPC classification number: H04L12/66 ,  H04L12/4135 ,  H04L12/4625 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map-The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.

Abstract translation: 用于执行通信信道之间的帧数据的传送控制的网关装置包括：路由映射，其存储关于帧数据的ID信息和关于使用ID信息的通信信道的信息;以及搜索引擎单元，其将帧数据路由到传送 基于接收到的帧数据的ID信息和路由映射来确定目的地。当关于接收到的帧数据的ID信息是未使用的ID信息时，搜索引擎单元不将帧数据传送到传送目的地 通信信道，通过它接收帧数据。

公开(公告)号：EP1916813A2

公开(公告)日：2008-04-30

申请号：EP07119414.6

申请日：2007-10-26

Applicant: FUJITSU TEN LIMITED ,  FUJITSU LIMITED ,  Renesas Technology Corp.

Inventor： Noumi, Kaoru, c/o FUJITSU TEN LIMITED ,  Nishihashi, Susumu, c/o FUJITSU TEN LIMITED ,  Katou, Tomoyuki, c/o FUJITSU TEN LIMITED ,  Ishikawa, Yukio, c/o FUJITSU TEN LIMITED ,  Umezaki, Yasuyuki, c/o Fujitsu Limited ,  Ebeshu, Hidetaka, c/o Fujitsu Limited ,  Koide, Shigeo, c/o Fujitsu Limited ,  Fujisawa, Yukio, c/o Renesas Technology Corp. ,  Shimauchi, Hiroaki, c/o Renesas Technology Corp.

IPC: H04L12/66

CPC classification number: H04L12/66 ,  H04L12/4135 ,  H04L12/4625 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map-The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.

Abstract translation: 用于在通信信道之间执行帧数据的传送控制的网关装置包括存储关于帧数据的ID信息和关于使用该ID信息的通信信道的信息的路由图，以及将帧数据路由到传送的搜索引擎单元 基于接收到的帧数据的ID信息和路由映射的目的地 - 当接收到的帧数据的ID信息是ID信息时，搜索引擎单元不将帧数据传送到传送目的地， 接收帧数据的通信信道。

公开(公告)号：EP1916794A2

公开(公告)日：2008-04-30

申请号：EP07119334.6

申请日：2007-10-25

Applicant: FUJITSU TEN LIMITED ,  FUJITSU LIMITED ,  Renesas Technology Corp.

Inventor： Noumi, Kaoru, c/o FUJITSU TEN LIMITED ,  Nishihashi, Susumu, c/o FUJITSU TEN LIMITED ,  Katou, Tomoyuki, c/o FUJITSU TEN LIMITED ,  Ishikawa, Yukio, c/o FUJITSU TEN LIMITED ,  Umezaki, Yasuyuki, c/o Fujitsu Limited ,  Ebeshu, Hidetaka, c/o Fujitsu Limited ,  Koide, Shigeo, c/o Fujitsu Limited ,  Fujisawa, Yukio, c/o Renesas Technology Corp. ,  Shimauchi, Hiroaki, c/o Renesas Technology Corp.

IPC: H04L1/00

CPC classification number: H04L1/0045 ,  G06F11/10 ,  H04L1/0063 ,  H04L1/243 ,  H04L1/244

Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Abstract translation: 错误检测器具有产生从CPU I / F发送到存储器的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及 选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。 当选择器电路切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，错误检测器进行错误检测功能的故障诊断，包括奇偶位产生器和奇偶校验器中的至少一个 。

公开(公告)号：EP1513043A3

公开(公告)日：2007-08-01

申请号：EP04254222.5

申请日：2004-07-14

Applicant: Renesas Technology Corp.

Inventor： Nishizawa, Hirotaka Renesas Technology Corp. ,  Higuchi, Akira Renesas Technology Corp. ,  Osawa, Kenji Renesas Technology Corp. ,  Wada, Tamaki Renesas Technology Corp. ,  Sugiyama, Michiaki Renesas Technology Corp. ,  Osako, Junichiro Renesas Technology Corp.

IPC: G06F1/00 ,  G06K19/077

CPC classification number: G06K19/077 ,  G06K19/07732 ,  H01L23/5388 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a memory card equipped with an interface controller connected to external connecting terminals, a memory connected to the interface controller, and a security controller connected to the interface controller. A second external connecting terminal capable of supplying an operating power supply to the security controller is provided aside from a first external connecting terminal which supplies an operating power supply to the interface controller and the memory. An interface unit of the interface controller connected to the security controller receives the operating power supply from the second external connecting terminal and thereby enables a stop of the supply of the operating power supply from the first external connecting terminal. Even if the supply of the operating power supply to the interface controller is cut off, the output of the interface unit is not brought to an indefinite state.

公开(公告)号：EP1806788A2

公开(公告)日：2007-07-11

申请号：EP06026218.5

申请日：2006-12-18

Applicant: Renesas Technology Corp.

Inventor： Ishigaki, Takashi, c/o Hitachi Ltd. ,  Osabe, Taro, c/o Hitachi Ltd. ,  Kobayashi, Takashi, c/o Hitachi Ltd. ,  Imai, Yutaka, c/o Renesas Tech. Corp. ,  Shimizu, Masahiro, c/o Renesas Tech. Corp.

IPC: H01L29/788 ,  H01L21/336 ,  H01L27/115

CPC classification number: H01L29/7881 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device comprises a floating gate which is formed on a semiconductor substrate of a first conductive type interposing a first gate insulation layer therebetween, a second charge retaining area which is formed on the semiconductor substrate interposing a second insulation layer, a control gate which is formed on the floating gate interposing a second gate insulation layer therebetween, a second gate electrode which extends in the first direction and which is formed on the second charge retaining region interposing the second gate insulation layer therebetween, and a semiconductor layer which extends in a second direction and which is formed on the semiconductor substrate so as to intersect the first and the second gate electrode are provided; wherein an n-type conductive region of a second conductive type is formed on the semiconductor layer. Consequently, it achieves high-integration of a semiconductor device.

Abstract translation: 半导体器件包括浮置栅极，其形成在其间插入第一栅极绝缘层的第一导电类型的半导体衬底上，形成在插入第二绝缘层的半导体衬底上的第二电荷保持区域，控制栅极 形成在浮置栅极上，在其间插入第二栅极绝缘层的第二栅电极，第二栅电极，沿第一方向延伸并形成在第二栅极绝缘层之间的第二电荷保持区域上;以及半导体层，其在第二栅极绝缘层中延伸 并且形成在半导体基板上以与第一和第二栅电极相交的方向; 其中在所述半导体层上形成第二导电类型的n型导电区域。 因此，实现了半导体器件的高集成度。

公开(公告)号：EP1793424A1

公开(公告)日：2007-06-06

申请号：EP05765318.0

申请日：2005-07-04

Applicant: Renesas Technology Corp.

Inventor： MATSUZAKI, Nozomu, c/o HITACHI, LTD. ,  TERAO, Motoyasu, c/o HITACHI, LTD.

IPC: H01L27/10

CPC classification number: H01L27/101 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/1675

Abstract: In non-volatile storage device using a variable resistance material, when a crystal state and a noncrystalline state co-exists in the variable resistance material, a crystallization time is shorted, resulting in decrease of the time to maintain information stored. Heat radiation is not rapidly performed during rewriting and thus it takes a long time to complete the rewriting due to a low thermal conductivity of a material contacting the variable resistance material.
According to the present invention, a contact area between a variable resistance material and a lower electrode, and a contact area between the variable resistance material and an upper electrode are made equal to each other, thereby unifying a current path. The invention provides a structure in which a material having a high thermal conductivity is disposed so as to contact a sidewall of the variable resistance material, and its end portion is made to contact the lower electrode as well.

Abstract translation: 在使用可变电阻材料的非易失性存储装置中，当晶体状态和非结晶状态在可变电阻材料中共存时，结晶时间短路，导致维持信息存储的时间减少。 在重写期间热辐射不会迅速进行，因此由于与可变电阻材料接触的材料的低导热性，完成重写需要很长时间。 根据本发明，可变电阻材料和下电极之间的接触面积和可变电阻材料与上电极之间的接触面积彼此相等，从而使电流通路一致。 本发明提供了一种结构，其中设置具有高导热性的材料以便接触可变电阻材料的侧壁，并且其端部也与下电极接触。

公开(公告)号：EP1755165A1

公开(公告)日：2007-02-21

申请号：EP05741426.0

申请日：2005-05-19

Applicant: Renesas Technology Corp.

Inventor： TAKEMURA, Riichiro Central Res. Lab. Hitachi, Ltd ,  KUROTSUCHI, Kenzo Central Res. Lab. Hitachi, Ltd ,  KAWAHARA, Takayuki Central Res. Lab. Hitachi, Ltd

IPC: H01L27/10 ,  G11C13/00

CPC classification number: H01L47/00 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

Abstract translation: 例如，使用两个存储单元晶体管和一个相变元件配置一个存储单元，通过将多个扩散层与位线平行地布置，在扩散层之间设置栅极以跨越位线，布置位 线接触和源触点交替地布置到针对每个扩散层的位线方向上的多个扩散层，以及在源极触点上提供相变元件。 此外，相位元件可以设置在位线触点上而不是源极触点。 通过这种方式，例如，可以实现存储单元晶体管的驱动性的提高和面积的减小。

公开(公告)号：EP1635217A1

公开(公告)日：2006-03-15

申请号：EP04807522.0

申请日：2004-12-22

Applicant: Renesas Technology Corp.

Inventor： TANAKA, Toshihiko, c/o Renesas Technology Corp.

IPC: G03F1/08 ,  H01L21/027

CPC classification number: G03F7/70425 ,  G03F7/70441

Abstract: A method of fabricating a semiconductor device including a first wiring pattern extending in a vertical direction and a second wiring pattern identical in geometry to the first wiring pattern and extending in a (horizontal) direction orthogonal to the vertical direction, including the steps of: employing linearly polarized illumination to perform exposure along a mask pattern including mask patterns (16, 17) used to form the first and second wiring patterns, respectively; and subsequently forming the first and second wiring patterns having a geometry along the mask patterns. The mask patterns to form the first and second wiring patterns are formed to be different in geometry.

Abstract translation: 一种半导体器件，其包括第一布线图案在垂直方向上延伸并在几何上的第一布线图案的第二布线相同的图案，并在（水平）方向垂直延伸的垂直方向上，包括以下步骤的制造方法：用人 线性偏振照明沿着掩模图案包含​​用于形成第一和第二布线图案，分别掩模图案（16，17）进行曝光; 并随后形成具有沿着所述掩模图案的几何形状的第一和第二布线图案。 掩模图案，以形成第一和第二布线图案形成为在不同的几何形状。

公开(公告)号：EP1619718A1

公开(公告)日：2006-01-25

申请号：EP04726313.2

申请日：2004-04-07

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  Renesas Technology Corp.

Inventor： Matsumoto, Susumu ,  Sekiguchi, Mitsuru ,  Nishioka, Yasutaka, c/o Renesas Technology Corp. ,  Tomita, Kazuo, c/o Renesas Technology Corp. ,  Iwasaki, Akihisa ,  Hashimoto, Keiji, c/o Renesas Technology Corp.

IPC: H01L21/768 ,  H01L21/316 ,  H01L21/027

CPC classification number: H01L21/76801 ,  H01L21/0274 ,  H01L21/3144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76835

Abstract: A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric constant film with a second nitrogen-non-containing insulating film interposed therebetween.

Abstract translation: 第一含氮绝缘膜形成在其中形成有通孔的低介电常数膜之下，其中第一含氮绝缘膜介于第一含氮绝缘膜和低介电常数膜之间。 第二含氮绝缘膜形成在低介电常数膜上，其间插入第二不含氮的绝缘膜。