公开(公告)号：EP1806788A2

公开(公告)日：2007-07-11

申请号：EP06026218.5

申请日：2006-12-18

Applicant: Renesas Technology Corp.

Inventor： Ishigaki, Takashi, c/o Hitachi Ltd. ,  Osabe, Taro, c/o Hitachi Ltd. ,  Kobayashi, Takashi, c/o Hitachi Ltd. ,  Imai, Yutaka, c/o Renesas Tech. Corp. ,  Shimizu, Masahiro, c/o Renesas Tech. Corp.

IPC: H01L29/788 ,  H01L21/336 ,  H01L27/115

CPC classification number: H01L29/7881 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device comprises a floating gate which is formed on a semiconductor substrate of a first conductive type interposing a first gate insulation layer therebetween, a second charge retaining area which is formed on the semiconductor substrate interposing a second insulation layer, a control gate which is formed on the floating gate interposing a second gate insulation layer therebetween, a second gate electrode which extends in the first direction and which is formed on the second charge retaining region interposing the second gate insulation layer therebetween, and a semiconductor layer which extends in a second direction and which is formed on the semiconductor substrate so as to intersect the first and the second gate electrode are provided; wherein an n-type conductive region of a second conductive type is formed on the semiconductor layer. Consequently, it achieves high-integration of a semiconductor device.

Abstract translation: 半导体器件包括浮置栅极，其形成在其间插入第一栅极绝缘层的第一导电类型的半导体衬底上，形成在插入第二绝缘层的半导体衬底上的第二电荷保持区域，控制栅极 形成在浮置栅极上，在其间插入第二栅极绝缘层的第二栅电极，第二栅电极，沿第一方向延伸并形成在第二栅极绝缘层之间的第二电荷保持区域上;以及半导体层，其在第二栅极绝缘层中延伸 并且形成在半导体基板上以与第一和第二栅电极相交的方向; 其中在所述半导体层上形成第二导电类型的n型导电区域。 因此，实现了半导体器件的高集成度。