公开(公告)号：US20210203226A1

公开(公告)日：2021-07-01

申请号：US17200498

申请日：2021-03-12

Applicant: STMicroelectronics (Alps) SAS

Inventor： Patrik Arno

IPC: H02M3/156

Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.

公开(公告)号：US11005490B2

公开(公告)日：2021-05-11

申请号：US16918940

申请日：2020-07-01

Applicant: STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Stéphane Le Tual ,  David Duperray ,  Jean-Pierre Blanc

IPC: H03M1/12 ,  H01L29/78 ,  G11C27/02

Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.

公开(公告)号：US10984845B2

公开(公告)日：2021-04-20

申请号：US16729056

申请日：2019-12-27

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Diana Moisuc ,  Christophe Laurencin

IPC: G11C8/20 ,  G11C16/22 ,  H04B3/52

Abstract: In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable.

公开(公告)号：US20210067177A1

公开(公告)日：2021-03-04

申请号：US17010351

申请日：2020-09-02

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice ROMAIN ,  Mathieu LISART ,  Patrick Arnould

IPC: H03M13/29 ,  G06F11/10

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

公开(公告)号：US20210019448A1

公开(公告)日：2021-01-21

申请号：US16928901

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (ALPS) SAS

Inventor： Marc BENVENISTE ,  Fabien JOURNET ,  Fabrice MARINET

IPC: G06F21/75 ,  G06F21/44 ,  H04L9/32 ,  G06F1/08 ,  G06F3/12

Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.

公开(公告)号：US20210006256A1

公开(公告)日：2021-01-07

申请号：US16918940

申请日：2020-07-01

Applicant: STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Stéphane Le Tual ,  David Duperray ,  Jean-Pierre Blanc

IPC: H03M1/12 ,  H01L29/78

Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.

公开(公告)号：US20200212927A1

公开(公告)日：2020-07-02

申请号：US16709391

申请日：2019-12-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Stephane LE TUAL ,  Jean-Pierre BLANC ,  David DUPERRAY

IPC: H03M1/68 ,  H03M1/06

Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.

公开(公告)号：US20200211607A1

公开(公告)日：2020-07-02

申请号：US16729056

申请日：2019-12-27

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Diana Moisuc ,  Christophe Laurencin

IPC: G11C8/20 ,  G11C16/22 ,  H04B3/52

Abstract: In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable.

公开(公告)号：US10673447B2

公开(公告)日：2020-06-02

申请号：US16269303

申请日：2019-02-06

Applicant: STMicroelectronics (Alps) SAS

Inventor： Laurent Vaccariello

IPC: H03M1/66 ,  H03M1/00 ,  H03M1/46 ,  H03M1/06 ,  H03M1/80 ,  H03M1/12 ,  H03M1/36

Abstract: An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.

公开(公告)号：US10607949B2

公开(公告)日：2020-03-31

申请号：US15607780

申请日：2017-05-30

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Yves Mazoyer ,  Philippe Galy ,  Philippe Sirito-Olivier

IPC: H01L23/60 ,  H01L23/62 ,  H01L27/02

Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.