公开(公告)号：DE69123100D1

公开(公告)日：1996-12-19

申请号：DE69123100

申请日：1991-08-21

Applicant: AT & T GLOBAL INF SOLUTION ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC FORT COLLINS

Inventor： CRAFTS HAROLD S ,  WALDRON ROBERT D

IPC: H03K3/356 ,  H03K3/3562

Abstract: A high speed CMOS clocked D-type flip-flop circuit (200) includes a master section (210) having input terminals (201, 203) adapted to receive D and D/ inputs and having parallel output terminals (247, 249) coupled to inputs of a slave section (220) which provides Q and Q/ outputs on Q and Q/ flip-flop output terminals (205, 207). The master and slave sections (210, 220) each include four CMOS tristate inverters (212-218; 222-228). The provision of parallel data paths having a small number of gates therein enables high-speed flip-flop operation to be achieved. A clock generating circuit (230) which may be selectively enabled generates true and complementary clock signals for the flip-flop circuit (200). In a modification, provision is made for a RESET signal to reset the flip-flop circuit (200).

公开(公告)号：DE69426407D1

公开(公告)日：2001-01-18

申请号：DE69426407

申请日：1994-10-10

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： TEENE ANDRES R

IPC: G01R31/28 ,  G01R31/30 ,  H01L21/66 ,  G06F11/24 ,  G06F11/26

Abstract: Current monitoring cells (12) are located at selected locations on power supply lines (16) within a chip. Each cell (12) compares the current flow at predetermined times with a reference. If the current exceeds the reference, a signal is provided indicating a fault in the chip. A flip flop (30) in the cell is set to maintain an indication of the fault condition. In two embodiments, the cells are connected with a scan chain which is used to sequentially access the test results for each cell. A third embodiment does not include the scan chain but the cells (12) are individually selectable. A current divider (56) may be included in each cell to isolate the voltage drop of the fault sensor from the functional circuit to minimize the impact of measuring the current for fault detection purposes.

公开(公告)号：AU5522898A

公开(公告)日：1999-06-28

申请号：AU5522898

申请日：1997-12-10

Applicant: SYMBIOS LOGIC INC

Inventor： DEKONING RODNEY A ,  GATES DENNIS E ,  BINFORD CHARLES D

IPC: G06F11/10

公开(公告)号：DE69409602T2

公开(公告)日：1998-12-17

申请号：DE69409602

申请日：1994-08-26

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： DULAC KEITH BERNARD

IPC: G06F12/08 ,  G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G11C29/00 ,  G06F13/40

Abstract: A data storage system comprises a matrix of intelligent storage nodes interconnected to communicate with each other via a network of busses (Ro-Rm,Co-Cn). The network of busses includes a plurality of first busses (Ro-Rm) for conducting data from and to a corresponding plurality of host system processors (Ho-Hm) and a plurality of second busses (Co-Cn), each one of the second busses intersecting with each one of the first busses. The nodes are located at each intersection. The storage nodes each include a data storage device (D), such as a magnetic disk drive unit, a processor (P) and buffer memory (B1-B3), whereby the node processor controls the storage and retrieval of data at the node as well as being capable of co-ordinating the storage and retrieval of data at other nodes within the network.

公开(公告)号：DE69314732T2

公开(公告)日：1998-07-23

申请号：DE69314732

申请日：1993-08-25

Applicant: HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC ,  NCR INT INC

Inventor： CRAFTS HAROLD S ,  MCKINLEY WILLIAM W

IPC: H03K19/173 ,  H03K19/177

公开(公告)号：AU5249198A

公开(公告)日：1998-06-03

申请号：AU5249198

申请日：1997-11-10

Applicant: SYMBIOS LOGIC INC

Inventor： KEMP STEVEN R ,  WHITEHILL CLIFFORD A ,  POEPPLEMAN ALAN D

IPC: G06F11/36 ,  G06F11/00

Abstract: A virtual monitor controller includes a data storage device coupled to receive and output data; an instruction storage device coupled to receive and output instructions; a status storage device coupled to receive and output status data; and a mode storage device coupled to receive and output mode data. The virtual monitor controller is included in a debugger/monitor controller. A debugger/monitor system comprises a host system; the debugger/monitor controller; and a digital processor. Preferably, the controller is coupled between the processor and IC logic. A method of operating a virtual monitor comprises the steps of intercepting an instruction fetch from a microprocessor; downloading instructions from a host computer; and operating the microprocessor with the instructions. Preferably, the instructions are sequentially downloaded.

公开(公告)号：NO980511L

公开(公告)日：1998-02-11

申请号：NO980511

申请日：1998-02-06

Applicant: SYMBIOS LOGIC INC

Inventor： DULAC KEITH BERNARD ,  FREEMAN PAUL MICHAEL

IPC: H04N5/93 ,  H04N7/173 ,  H04N21/472

Abstract: An apparatus for storing and playing videos. The apparatus includes a storage device containing a video for playback on a user system located on a communications network. The apparatus includes a system connection to a data processing system and a network connection to the communications network. The apparatus includes a transfer means for transferring the video from the storage device to the network using the network connection, wherein the video is directly transferred from the apparatus to the network.

公开(公告)号：DE69220134T2

公开(公告)日：1998-01-29

申请号：DE69220134

申请日：1992-03-11

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： JIBBE MAHMOUD K ,  MCCOMBS CRAIG C

IPC: G06F3/06 ,  G06F9/48 ,  G06F13/24

Abstract: A system interrupt signal for a disk array is generated by selectively combining interrupt signals received from individual disk drives and other interrupt signal sources within the disk array. The circuit for generating the system interrupt signal includes a first logic circuit (140) for combining a first group of selected interrupt signals to generate a group interrupt signal having an active state when each one of the signals in the first group is at an active state, and a second logic circuit (120) which combines a second group of selected interrupt signals to generate an independent interrupt signal having an active state when any one of the interrupt signals of the second group has an active state. The group and independent interrupt signals are gated together to generate a common system interrupt signal. The first and second logic circuits (120,140) can be reconfigured to combine, pass or ignore interrupt signals as selected by the system user. The circuit includes filtering and latching circuits (160,170) to prevent interference with an existing array interrupt signal during reconfiguration of the group or independent interrupt logic circuits (120,140).

公开(公告)号：AU3184797A

公开(公告)日：1998-01-21

申请号：AU3184797

申请日：1997-06-23

Applicant: SYMBIOS LOGIC INC

Inventor： TABOR GREGORY A ,  JANDER MARK J

IPC: H03K3/03 ,  H03K5/13 ,  H03L7/099 ,  H03K19/003 ,  G06F13/40

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

公开(公告)号：DE69405442D1

公开(公告)日：1997-10-16

申请号：DE69405442

申请日：1994-03-17

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： CRAFTS HAROLD S

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0175 ,  H03H7/38

Abstract: An I/O transceiver circuit, suitable for use on each integrated circuit of a multi-chip module, controls the output resistance of the transmitter portion (20). Control of the output resistance is achieved by a phase-locked-loop arrangement which includes a phase detector (102) a charge pump (106), a low-pass filter (108), a voltage controller (110) and a voltage controlled oscillator (120). Control of the output resistance allows operation without characteristically terminated I/O lines between multi-chip modules, thereby saving power otherwise wasted in the terminating resistors.