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166 records (took 0.031 seconds)

    115.
    外观设计
    有权

    公开(公告)号：KR3006190450000S

    公开(公告)日：2011-11-02

    申请号：KR3020100030680

    申请日：2010-07-13

    Applicant: 삼성전자주식회사

    Designer： 김주형

    플래시 메모리 장치 및 그것을 포함한 메모리 시스템
    117.
    发明公开
    플래시 메모리 장치 및 그것을 포함한 메모리 시스템 有权
    闪存存储器件和包括其的存储器系统

    公开(公告)号：KR1020110053798A

    公开(公告)日：2011-05-24

    申请号：KR1020090110473

    申请日：2009-11-16

    Applicant: 삼성전자주식회사

    Inventor： 김주형 ,  강창석 ,  박영우 ,  최정달 ,  김종연

    IPC: G11C16/22 ,  G11C16/00

    CPC classification number: G06F11/1068 ,  G11C2029/0411 ,  G11C16/22 ,  G11C16/00

    Abstract: PURPOSE: A flash memory device and a memory system including the same are provided to improve the reliability of security data by programming security data with a wafer level and a package level. CONSTITUTION: In a flash memory device and a memory system including the same, a row decoder circuit(1200) selects and drives the rows of a memory cell array(1100). A voltage generating circuit(1300) is controlled by a control logic(1600). The generated voltages are supplied to the memory cell array. A reading / write circuit(1400) reads data from the selected memory cells. An input-output circuit(1500) interfaces data between the read/write circuit and an external device.

    Abstract translation: 目的：提供一种闪存设备和包括该闪存设备的存储器系统，以通过利用晶片级和封装级编程安全数据来提高安全数据的可靠性。 构成：在闪速存储器件和包括其的存储器系统中，行解码器电路（1200）选择并驱动存储单元阵列（1100）的行。 电压发生电路（1300）由控制逻辑（1600）控制。 所产生的电压被提供给存储单元阵列。 读/写电路（1400）从所选存储单元读取数据。 输入 - 输出电路（1500）在读/写电路和外部设备之间接口数据。

    반도체소자 및 그 제조방법
    119.
    发明公开
    반도체소자 및 그 제조방법 有权
    半导体器件及其制造方法

    公开(公告)号：KR1020100061017A

    公开(公告)日：2010-06-07

    申请号：KR1020080119886

    申请日：2008-11-28

    Applicant: 삼성전자주식회사

    Inventor： 김주형 ,  강창석 ,  장성일 ,  박영우 ,  최정달

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/4234

    Abstract: PURPOSE: A semiconductor device and a fabrication method thereof are provided to improve an erase operation of a flash memory device by reducing an electron back-tunneling due to electric filed at the edge of a conductive pattern. CONSTITUTION: A first dielectric pattern(5a), a data storage pattern(10a), and a second dielectric pattern(15a) are successively laminated on a semiconductor substrate(1). A first conductive pattern(20b) is formed on the second dielectric pattern. The second conductive pattern(25a) is formed on the first conductive pattern. The second conductive pattern has the width bigger than the first conductive pattern. The second dielectric pattern has the width bigger than the first conductive pattern. The first and second conductive patterns comprise different conductive material films.

    Abstract translation: 目的：提供半导体器件及其制造方法，以通过减少由导电图案的边缘处的电场引起的电子反向隧穿来改善闪存器件的擦除操作。 构成：在半导体衬底（1）上依次层叠第一电介质图案（5a），数据存储图案（10a）和第二电介质图案（15a）。 第一导电图案（20b）形成在第二电介质图案上。 第二导电图案（25a）形成在第一导电图案上。 第二导电图案的宽度大于第一导电图案。 第二电介质图案的宽度大于第一导电图案。 第一和第二导电图案包括不同的导电材料膜。

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