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公开(公告)号：KR1020040033157A
公开(公告)日：2004-04-21
申请号：KR1020020062075
申请日：2002-10-11
Applicant: 한국전자통신연구원
IPC: H04B1/40
CPC classification number: G06K19/0723
Abstract: PURPOSE: An RFID(Radio Frequency Identification) and a method for operating the same are provided to configure a special logic circuit that processes signals to control the operations of an RFID. CONSTITUTION: An RFID comprises an antenna(100), an analog signal processing part(110), a digital signal processing part(120), and a logic operation part(130). The antenna(100) transmits and receives signals with an external devices. The analog signal processing part(110) converts an analog signal, received to the antenna(100), into a digital signal. Also the analog signal processing part(110) converts a digital signal to be transmitted to the external device into an analog signal and transmits it to the antenna(100). The digital signal processing part(120) receives a digital signal from the analog signal processing part(110), demodulates the received signal, and detects an SOF(Start Of Frame) signal and an EOF(End Of Frame) signal. The logic operation part(130) comprises a memory unit and a logic processing unit to process the data transmitted and received with the external device.
Abstract translation: 目的：提供RFID（射频识别）及其操作方法，以配置处理信号以控制RFID操作的特殊逻辑电路。 构成：RFID包括天线（100），模拟信号处理部分（110），数字信号处理部分（120）和逻辑运算部分（130）。 天线（100）利用外部设备发送和接收信号。 模拟信号处理部分（110）将接收到天线（100）的模拟信号转换为数字信号。 此外，模拟信号处理部分（110）将要发送到外部设备的数字信号转换成模拟信号并将其发送到天线（100）。 数字信号处理部（120）从模拟信号处理部（110）接收数字信号，对接收到的信号进行解调，并检测出SOF（起始帧）信号和EOF（帧结束）信号。 逻辑运算部分（130）包括存储器单元和逻辑处理单元，用于处理与外部设备发送和接收的数据。
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112.发明授权무선 공개키 기반 구조에서의 인증서 발급 요청/처리 장치및 그 방법과 그를 이용한 인증서 발급 시스템 失效무선공개키기반구조에서의인증서발급요청/처리장치및그방법과그를이용인서발급시스템
公开(公告)号：KR100406525B1
公开(公告)日：2003-11-22
申请号：KR1020010040971
申请日：2001-07-09
Applicant: 한국전자통신연구원
IPC: H04L9/30
Abstract: PURPOSE: An authentication issue request/process apparatus and method in a wireless public key infrastructure, and an authentication issue system using the same are provided to issue an authentication in the wireless public key infrastructure by a message signature function like a wireless markup language script sign text. CONSTITUTION: An authentication issue request device(100) signs an authentication request message using a user' identification, password, a signature public key, and a signature authentication and transmits it to an authentication issue processor(200) through a wireless network. The authentication issue request device(100) includes an initial information input/generation and providing module(110), an authentication request message generating module(120), an authentication request message signature module(130), and an authentication request control module(140). The authentication issue processor(200) tests and processes the signed authentication request message of the authentication issue request device(100). The authentication issue processor(200) includes an authentication request message signature testing module(210) and an authentication request message process module(220).
Abstract translation: 目的：提供一种无线公钥基础设施中的验证问题请求/处理设备和方法，以及使用该验证问题系统的验证问题系统，以通过消息签名功能（如无线标记语言脚本标记）在无线公钥基础设施中发布验证 文本。 组成：认证发布请求设备（100）使用用户的标识，密码，签名公共密钥和签名认证来签署认证请求消息，并通过无线网络将其发送到认证发布处理器（200）。 认证发行请求装置（100）包括初始信息输入/生成和提供模块（110），认证请求消息生成模块（120），认证请求消息签名模块（130）和认证请求控制模块（140） ）。 认证问题处理器（200）测试并处理认证问题请求设备（100）的签名认证请求消息。 认证问题处理器（200）包括认证请求消息签名测试模块（210）和认证请求消息处理模块（220）。
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公开(公告)号：KR1020030048243A
公开(公告)日：2003-06-19
申请号：KR1020010078127
申请日：2001-12-11
Applicant: 한국전자통신연구원
IPC: G06F7/44
Abstract: PURPOSE: A device for a modular multiplication is provided to execute a modular multiplication at high speed by repeating a bit multiplication and executing a modular multiplication of data more than a specific bit, thereby reducing a circuit area of a modular multiplication device, and a reducing memory accessing times using a register for storing a mid-point. CONSTITUTION: A memory(160) stores data for executing a modular multiplication of information. A processor requests the modular multiplication and loads/uses the multiplication results from the memory(160). A register(230) receives data for a modular multiplication from the memory(160), stores the data, and stores a mid-point being generated during the modular multiplication. A modular circuit(240) repeats a bit multiplication calculation, executes a modular multiplication of data which are greater than a specific bit, and stores a mid-point in the register(230) and a result value in the memory(160). A reduction circuit(250) corrects the result value selectively in accordance with a comparison result of the result value and the modular value. A control circuit(220) outputs various kinds of control signals to the register(230), the modular circuit(240), and the reduction circuit(250), and controls the modular multiplication.
Abstract translation: 目的：提供一种用于模乘的装置，通过重复比特乘法和执行比特定比特数据的模数乘法，高速执行模乘法，从而减少了乘法装置的电路面积，并减少了 使用寄存器存储中点的存储器存取时间。 构成：存储器（160）存储用于执行信息的模数乘法的数据。 处理器请求模乘，并加载/使用来自存储器的乘法结果（160）。 寄存器（230）从存储器（160）接收用于模数乘法的数据，存储数据，并存储在模乘期间生成的中点。 模块化电路（240）重复位乘法计算，执行大于特定位的数据的模乘，并将寄存器（230）中的中点和结果值存储在存储器（160）中。 还原电路（250）根据结果值和模块值的比较结果有选择地校正结果值。 控制电路（220）向寄存器（230），模块电路（240）和还原电路（250）输出各种控制信号，并控制模乘。
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公开(公告)号：KR1020030024100A
公开(公告)日：2003-03-26
申请号：KR1020010057083
申请日：2001-09-17
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: PURPOSE: A smart card emulator and an emulation method thereof are provided to effectively develop a contact/non-contact smart card and a USB(Universal Serial Bus) card through the simple design modification of a hardware logic. CONSTITUTION: The smart card emulator includes a computer(100), a controlling block(202), two ports(204,208), the first memory block(206), the second memory block(210), a clock generating block(212), a signal processing block(214) and an interface block(216). The controlling block(202) performs entire control needed to perform the emulation of the smart card. The first memory block(206) stores a VHDL(VHSIC(Very High Speed IC) Hardware Description Language) code needed to design the hardware logic. The second memory block(210) comprises an SRAM reading and writing the contents according to the execution of the emulator, a ROM storing an OS(Operating System) program of the emulator and an EEPROM(Electronically Erasable Programmable ROM) storing various application programs. The signal processing block(214) is an FPGA(Field Programmable Gate Array) for realizing a user defined additional function module.
Abstract translation: 目的：提供智能卡仿真器及其仿真方法，通过硬件逻辑的简单设计修改来有效地开发接触/非接触智能卡和USB（通用串行总线）卡。 构成：智能卡仿真器包括计算机（100），控制块（202），两个端口（204,208），第一存储块（206），第二存储器块（210），时钟生成块（212） 信号处理块（214）和接口块（216）。 控制块（202）执行执行智能卡仿真所需的全部控制。 第一存储器块（206）存储设计硬件逻辑所需的VHDL（VHSIC（超高速IC）硬件描述语言）代码。 第二存储器块（210）包括根据仿真器的执行读取和写入内容的SRAM，存储仿真器的OS（操作系统）程序的ROM和存储各种应用程序的EEPROM（电可擦除可编程ROM）。 信号处理块（214）是用于实现用户定义的附加功能模块的FPGA（现场可编程门阵列）。
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公开(公告)号：KR1020020095937A
公开(公告)日：2002-12-28
申请号：KR1020010034306
申请日：2001-06-18
Applicant: 한국전자통신연구원
IPC: G09C1/00
Abstract: PURPOSE: An ellipse curve encryption device is provided to have a high security with maintaining a short key so as to authenticate a user in a system restricted in area such as an integrated(IC) card and to exchange the key values of the symmetric key system. CONSTITUTION: An ellipse curve encryption device includes a first storing register(201) for storing operational coefficient values of an ellipse curve encryption, a second storing register(202) for storing input values of operation for the ellipse curve encryption, an ellipse curve encryption operation module(205) for implementing the ellipse curve encryption operation by using the valued stored at the first and the second registers(201,202), a third register(203) for inputting to the ellipse curve encryption operation module(205) so as to use the following operation after the output value form the ellipse curve encryption operation module is stored at the register and an ellipse curve encryption controller(204) for controlling the ellipse curve encryption operation module(205) in response to the value stored the first register(201) and for managing the transmission of the operation result.
Abstract translation: 目的：提供一种椭圆曲线加密装置，具有保持短密钥的高安全性，以便对诸如集成（IC）卡等区域限制的系统中的用户进行认证，并交换对称密钥系统的密钥值 。 构成：椭圆曲线加密装置包括用于存储椭圆曲线加密的运算系数值的第一存储寄存器（201），用于存储用于椭圆曲线加密的输入值的第二存储寄存器（202），椭圆曲线加密运算 模块（205），用于通过使用在第一和第二寄存器（201,202）处存储的值来实现椭圆曲线加密操作;第三寄存器（203），用于输入到椭圆曲线加密操作模块（205），以便使用 在输出值形成椭圆曲线加密操作模块之后的以下操作被存储在寄存器和用于响应于存储第一寄存器（201）的值的控制椭圆曲线加密操作模块（205）的椭圆曲线加密控制器（204） 并且用于管理操作结果的传输。
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Patent Agency Ranking
公开(公告)号：KR1020020079144A
公开(公告)日：2002-10-19
申请号：KR1020010019861
申请日：2001-04-13
Applicant: 한국전자통신연구원
IPC: G06F7/00
Abstract: PURPOSE: A device and a method for multiplying the finite fields on a polynomial basis are provided to offer a small volume circuit by using a digit serial mode in the finite fields multiplication of high degree polynomial and to realize the fast multiplication by using a fast clock generator deferent from the system clock. CONSTITUTION: The first storing tool stores a multiplier, a multiplicand and a product as the operation result by dividing into a digit unit. The second storing tool(15) assists the operation by storing a middle value necessary for a process carrying out the operation in the first storing tool and stores the final result. An address generating tool(16) generates an address of the second storing tool for writing or reading the value necessary for the first storing tool from the second storing tool. A clock generating tool(17) provides the fast clock operated by being separated from the system clock to the first storing tool.
Abstract translation: 目的：提供一种用于在多项式基础上乘以有限域的装置和方法，通过在高次多项式的有限域乘法中使用数字串行模式来提供小体积电路，并通过使用快速时钟来实现快速乘法 发电机不同于系统时钟。 构成：第一存储工具将乘法器，乘法器和乘积作为运算结果分成数位单元。 第二存储工具（15）通过将执行该操作的处理所需的中间值存储在第一存储工具中来存储最终结果来辅助操作。 地址生成工具（16）生成用于从第二存储工具写入或读取第一存储工具所需的值的第二存储工具的地址。 时钟产生工具（17）提供通过从系统时钟分离到第一存储工具来操作的快速时钟。
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公开(公告)号：KR1020160118094A
公开(公告)日：2016-10-11
申请号：KR1020150046426
申请日：2015-04-01
IPC: A63B22/02
Abstract: 본발명은다양한방향으로진행할수 있는이족운동장치를제공한다. 본발명의일 측면에따른이족운동장치는다각형상으로이루어진이족운동장치에있어서, 복수개의롤러들을포함하며, 연이어배치된복수개의롤 컨베이어와, 서로이웃하게배치된롤 컨베이어의롤러을연결하는커플링과, 상기롤러에설치된기어와상기기어와맞물리는웜을포함하는동력전달부재, 및상기웜과연결된구동축을회전시키는전동기를포함한다.
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公开(公告)号：KR101086046B1
公开(公告)日：2011-11-22
申请号：KR1020090019873
申请日：2009-03-09
Applicant: 한국전자통신연구원
Abstract: 본 발명은 유한 확장체에서 제곱근 계산 장치 및 방법에 관한 것이다.
유한 확장체 (여기서 p는 소수, k는 홀수)에서 임의의 소수 p에 대해 제곱근을 효율적으로 계산하기 위하여 지수승 계산을 위한 표현법을 새로 정의함으로써, 지수 연산에 필요한 연산량을 줄일 수 있어 향상된 알고리즘의 효율성을 가질 수 있다.
유한 확장체, 제곱근, 지수승, 임의의 소수, Tonelli-Shanks-
公开(公告)号：KR101014628B1
公开(公告)日：2011-02-16
申请号：KR1020080074615
申请日：2008-07-30
Applicant: 한국전자통신연구원
IPC: G01S13/04
Abstract: 본 발명은 감시 레이더를 이용한 선박 관제 시스템에 관한 것으로, 감시 레이더를 이용한 질의 및 응답 방식의 양방향 통신을 통해 관제 정보를 획득함으로써, 종래의 선박자동식별장치를 이용할 경우에 복잡한 해안 인접 지형과 산악 지형을 통과하는 연안 또는 내륙 운하에서의 선박 관제의 어려움과 비효율성을 제거함과 아울러 안정적이고 효율적인 선박 관제를 제공하며, 선박의 강제적인 트래픽 관리를 통해 선박 충돌의 위험을 사전에 방지할 수 있는 이점이 있다.
선박 운항 관제, 관제 정보, 감시 레이더, 관제 정보 질의, 관제 정보 해석
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