公开(公告)号：WO1997008624A1

公开(公告)日：1997-03-06

申请号：PCT/US1996012126

申请日：1996-07-23

Applicant: INTEL CORPORATION ,  PENDSE, Ajit ,  GELSINGER, Patrick

Inventor： INTEL CORPORATION

IPC: G06F13/00

CPC classification number: H04L67/16 ,  H04L29/06 ,  H04L67/28 ,  H04L67/2809 ,  H04L69/329 ,  H04M3/42068 ,  H04M3/42102 ,  H04M3/4211

Abstract: An on-line/information service system is constituted with a caller management server (20) and a number of on-line/information servers (22 and 24). The caller management server (20) is equipped with multiple ports and complementary hardware/software, including a call management application (228), for managing multiple concurrent calls, which includes optionally validating the calls depending on whether services are provided on a callee service provider or caller basis, assigning and connecting the calls to corresponding on-line/information service delivery environments on the on-line/information servers (22 and 24). The on-line/information servers (22 and 24) are equipped with adequate hardware/software including an on-line/information service manager application (316) and a number of on-line/information service applications (318), to support multiple on-line/information service delivery environments. Each on-line/information service delivery environment is equipped with streamlined application sharing host services, thereby allowing end-user PC (14) equipped with streamlined application sharing client services (128) to access on-line/information services provided by the on-line/information service applications.

Abstract translation: 在线/信息服务系统由呼叫者管理服务器（20）和多个在线/信息服务器（22和24）构成。 呼叫者管理服务器（20）配备有多个端口和补充硬件/软件，包括用于管理多个并发呼叫的呼叫管理应用（228），其包括可选地根据在被叫方服务提供商上提供服务来验证呼叫 或呼叫者基础，将呼叫分配和连接到在线/信息服务器（22和24）上的对应的在线/信息服务递送环境。 在线/信息服务器（22和24）配备有足够的硬件/软件，包括在线/信息服务管理器应用（316）和多个在线/信息服务应用（318），以支持多个 在线/信息服务交付环境。 每个在线/信息服务交付环境配备有简化的应用共享主机服务，从而允许配备简化应用共享客户端服务（128）的终端用户PC（14）访问在线/ 线/信息服务应用程序。

公开(公告)号：WO1997006486A1

公开(公告)日：1997-02-20

申请号：PCT/US1996012123

申请日：1996-07-23

Applicant: INTEL CORPORATION ,  LANEY, Clifton, W. ,  LESZCZYNSKI, Larry, M. ,  MADISON, Mary, J.

Inventor： INTEL CORPORATION

IPC: G06F11/00

CPC classification number: G06F9/4418

Abstract: A method of allowing an operating system of a computer system (20) to persist across a power off and on cycle is described. The method includes the step of detecting if the computer system (20) is to be powered off (51). If the computer system (20) is dectected to be powered off, the state of the computer system (20) is then preserved by storing data representing the state of the computer system (20) in a designated area of a nonvolatile memory (23, 54). A system initilization code of the operating system is then replaced with new system initialization code that branches to restart code that accesses to the designated area of the nonvolatile memory (23, 55) such that when the computer system (20) is again powered on, the restart code accesses the designated area of the nonvolatile memory (23) for the data to restore the computer system (20) to the state before it was powered off.

Abstract translation: 描述允许计算机系统（20）的操作系统在断电和开启周期上持续的方法。 该方法包括检测计算机系统（20）是否被断电的步骤（51）。 如果计算机系统（20）被检测为关闭电源，则通过将表示计算机系统（20）的状态的数据存储在非易失性存储器（23,23）的指定区域中来保存计算机系统（20）的状态， 54）。 操作系统的系统启动代码然后被新的系统初始化代码替换，该系统初始化代码分支以重新启动访问非易失性存储器（23,55）的指定区域的代码，使得当计算机系统（20）再次通电时， 重新启动代码访问用于数据的非易失性存储器（23）的指定区域，以将计算机系统（20）恢复到其断电之前的状态。

公开(公告)号：WO1997002594A1

公开(公告)日：1997-01-23

申请号：PCT/US1996011184

申请日：1996-07-01

Applicant: INTEL CORPORATION ,  THOMPSON, Scott ,  BOHR, Mark, T. ,  PACKAN, Paul, A.

Inventor： INTEL CORPORATION

IPC: H01L21/385

CPC classification number: H01L29/6659 ,  H01L21/2257 ,  H01L21/823814 ,  H01L29/6656

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region (40) immediately adjacent to the gate (11) and a more heavily doped main portion (41) of the source and drain region spaced apart from the gate. A first layer (16) of glass (2 % BSG) is used to provide the source of doping for the tip region and a second layer (35) of glass (6 % BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers (30, 31) are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

Abstract translation: 一种用于制造源极和漏极区域的工艺，其包括与栅极（11）紧邻的更轻掺杂的源极和漏极尖端区域（40），以及与源极和漏极区域间隔开的更重掺杂的主要部分（41） 大门。 使用玻璃（2％BSG）的第一层（16）提供尖端区域的掺杂源，并且使用玻璃（6％BSG）的第二层（35）提供掺杂剂用于更重掺杂 源区和漏区的主要部分。 在玻璃层之间形成间隔物（30,31），以从源区和漏区的主要部分限定尖端区域。

公开(公告)号：WO1996031101A1

公开(公告)日：1996-10-03

申请号：PCT/US1996001995

申请日：1996-02-15

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  KUHN, Harry, A. ,  MALLIK, Debendra ,  SETH, Ashok

IPC: H05K01/14

CPC classification number: H01L23/576 ,  G06K19/07372 ,  H01L25/18 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49171 ,  H01L2924/00

Abstract: An integrated circuit package which has a flexible circuit (12) that covers an integrated circuit (14). The flexible circuit (12) contains a conductive line (18) which prevents a probe (16) from accessing the integrated circuit (14). The conductive line (18) of the flexible circuit can be attached to the power lines, synchronization line, memory erase line, or any other line that will disable, erase or otherwise prevent access to the integrated circuit (14) if the flexible circuit conductive line is broken. The integrated circuit (14) can be mounted to a printed circuit board (15). The printed circuit board, integrated circuit and flexible circuit can all be enclosed within a package.

Abstract translation: 一种具有覆盖集成电路（14）的柔性电路（12）的集成电路封装。 柔性电路（12）包含防止探针（16）进入集成电路（14）的导线（18）。 柔性电路的导线（18）可以连接到电源线，同步线，存储器擦除线或任何其他线路，如果柔性电路导通，则禁用，擦除或以其他方式阻止对集成电路（14）的访问 线坏了 集成电路（14）可以安装到印刷电路板（15）上。 印刷电路板，集成电路和柔性电路都可以封装在封装内。

公开(公告)号：WO1996030831A1

公开(公告)日：1996-10-03

申请号：PCT/US1996002720

申请日：1996-02-29

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MURTHI, Raghu ,  TETRICK, Scott

IPC: G06F09/46

CPC classification number: G11C29/26

Abstract: Testing of shared memory (RAM) (10) in a multiple processor computer system is achieved by partitioning the memory (10) and allocating the memory portions to respective processors (20a-20d) in the system. Each processor (20a-20d) performs testing of its allocated memory portion simultaneously with the other processors in order to reduce the time required to complete the memory test.

Abstract translation: 通过划分存储器（10）并将存储器部分分配给系统中的相应处理器（20a-20d）来实现多处理器计算机系统中的共享存储器（RAM）（10）的测试。 每个处理器（20a-20d）与其他处理器同时执行其分配的存储器部分的测试，以便减少完成存储器测试所需的时间。

公开(公告)号：WO1996027280A1

公开(公告)日：1996-09-06

申请号：PCT/US1996002000

申请日：1996-02-15

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BANERJEE, Koushik ,  MALLIK, Debendra ,  SETH, Ashok

IPC: H05K07/20

CPC classification number: H01L23/642 ,  H01L23/13 ,  H01L23/142 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/0201 ,  H05K1/114 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10969 ,  H05K2203/0455 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated circuit package (10) which has internal bonding pads (46) that are located on bonding shelves and coupled to internal conductive power/ground planes (20, 24, 28) by conductive strips (52) that extend along the edges of the shelves. The edge strips eliminate the need for conventional vias to couple the bonding pads to the planes and thus reduce the cost and size of the package and improve package electrical performance (less inductive, less resistance path). The bonding pads are coupled to an integrated circuit (12) that is mounted to a heat slug (54) attached to a top surface of the package. The heat slug can function as both a ground path and a thermal sink for the integrated circuit. The package may have capacitors (62) coupled to the internal routing of the package to reduce the electrical noise of the signals provided to the integrated circuit. Additionally, the package may have multiple power planes dedicated to different voltage levels. The bonding pads and conductive planes are coupled to landing pads located on a bottom surface of the package. Attached to the landing pads are solder balls (68) which can be soldered to an external printed circuit board (72).

Abstract translation: 一种集成电路封装（10），其具有内部接合焊盘（46），所述接合焊盘位于结合搁架上并且通过导电条（52）连接到内部导电电力/接地平面（20,24,28），导电条（52）沿着 货架。 边缘条消除了对传统通孔的需要，以将接合焊盘耦合到平面，从而降低封装的成本和尺寸并提高封装电性能（较小的电感，较小的电阻路径）。 接合焊盘耦合到集成电路（12），该集成电路（12）安装到附接到封装的顶表面的散热块（54）。 散热片可用作集成电路的接地路径和散热片。 封装可以具有耦合到封装的内部布线的电容器（62），以减少提供给集成电路的信号的电噪声。 此外，封装可以具有专用于不同电压电平的多个电源层。 接合焊盘和导电平面耦合到位于封装的底表面上的着陆焊盘。 连接到着陆焊盘的是可以焊接到外部印刷电路板（72）的焊球（68）。

公开(公告)号：WO1996027206A2

公开(公告)日：1996-09-06

申请号：PCT/US1996001784

申请日：1996-02-07

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BOHR, Mark, T. ,  BRIGHAM, Lawrence, N. ,  MOON, Peter, K. ,  MORIMOTO, Seiichi

IPC: H01L00/00

CPC classification number: H01L21/3212 ,  H01L21/28123

Abstract: A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.

Abstract translation: 在制造高性能金属氧化物半导体（MOS）器件中使用标准图案化技术的多晶硅栅极图案化改进的抛光工艺。 在沉积之后和在多晶硅层的图案化之前添加短硅抛光步骤减少了通常与多晶硅相关的非平面性。 多晶硅抛光消除由多晶硅的晶粒结构引起的多晶硅层中的表面粗糙度以及由于隔离和衬底区域的底部形貌的复制所导致的表面粗糙度。 所描述的用于去除两种类型的表面粗糙度的方法使多晶硅层平坦化，而不增加已经与高性能MOS器件的制造相关联的缺陷水平。

公开(公告)号：WO1996026520A1

公开(公告)日：1996-08-29

申请号：PCT/US1996002410

申请日：1996-02-20

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  LARSEN, Robert, E. ,  DURANTE, Richard, J.

IPC: G11C07/00

CPC classification number: G11C7/1069 ,  G11C7/1051

Abstract: A nonvolatile memory (10) includes a memory array (11) and a buffer circuit (50) for applying data read from the memory array to external circuitry. A compensation circuit (51) is coupled to the buffer circuit for providing output compensation to the buffer circuit when enabled. The buffer circuit has (1) a first output speed when the compensation circuit is enabled and (2) a second output speed when the compensation circuit is disabled. A configuration circuit is coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured between the first and second output speeds. A method of configuring a nonvolatile memory between a first output speed and a second output speed is also described.

Abstract translation: 非易失性存储器（10）包括用于将从存储器阵列读取的数据施加到外部电路的存储器阵列（11）和缓冲电路（50）。 补偿电路（51）耦合到缓冲电路，用于在使能时向缓冲电路提供输出补偿。 缓冲电路具有（1）补偿电路使能时的第一输出速度和（2）补偿电路禁用时的第二输出速度。 配置电路耦合到补偿电路，用于选择性地启用补偿电路，使得可以在第一和第二输出速度之间配置缓冲电路。 还描述了在第一输出速度和第二输出速度之间配置非易失性存储器的方法。

公开(公告)号：WO1996025803A1

公开(公告)日：1996-08-22

申请号：PCT/US1996001313

申请日：1996-01-31

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHENG, King, Y.

IPC: H04B01/38

CPC classification number: H04L7/0029

Abstract: In a data transmission system (10), a method of synchronizing a digital signal to a remote clock signal at which the digital signal is processed and transmitted to the data transmission system (10) includes the step of selecting (32) a first set of filter coefficients from a plurality sets of filter coefficients for a digital filter (30). Each set of the plurality sets of filter coefficients corresponds to one of a plurality of timings (31). The first set of filter coefficients are then applied to the digital filter (30) for filtering the digital signal (X(n)). Timing (31) of the filtered digital signal is then detected. A second set of filter coefficients are selected from the plurality sets of filter coefficients and applied to the digital filter (30) in accordance with the detected timing of the filtered digital signal (Y(n)).

Abstract translation: 在数据传输系统（10）中，将数字信号与数字信号被处理并发送到数据传输系统（10）的远程时钟信号同步的方法包括以下步骤：选择（32）第一组 用于数字滤波器（30）的多组滤波器系数的滤波器系数。 多组滤波器系数中的每一组对应于多个定时（31）中的一个。 然后将第一组滤波器系数应用于数字滤波器（30），以对数字信号（X（n））进行滤波。 然后检测滤波后的数字信号的定时（31）。 从多个滤波器系数组中选择第二组滤波器系数，并根据检测到的滤波数字信号（Y（n））的定时将其应用于数字滤波器（30）。

公开(公告)号：WO1996025723A1

公开(公告)日：1996-08-22

申请号：PCT/US1996002126

申请日：1996-02-15

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  COELHO, Rohan, G., F. ,  PACKER, Alan ,  BALDES, Gary ,  FRANK, Davis, W. ,  GERGER, Richard ,  YEE, Wendy ,  JOHNSON, Louis ,  CRONIN, Thomas

IPC: G06T15/00

CPC classification number: G06T15/005 ,  H04N19/23 ,  Y10S707/99945 ,  Y10S707/99948

Abstract: A display mixer exports a first set of functions adapted to be called by one or more object libraries to create one or more generic objects. A surface/attribute manager exports a second set of functions adapted to be called by an application to manipulate the generic objects. The display mixer and the surface/attribute manager cause the generic objects to be rendered into a common draw surface. The display mixer and the surface/attribute manager manage a set of common attributes shared by the generic objects and manage attachments between the generic objects. A first object library calls a create-object function in the display mixer to create one or more first generic objects. The first object library generates display data for the first generic objects and the display mixer coordinates the display of the display data for the first generic objects.

Abstract translation: 显示混合器输出适于由一个或多个对象库调用以创建一个或多个通用对象的第一组函数。 表面/属性管理器导出适于由应用程序调用以操纵通用对象的第二组函数。 显示混合器和表面/属性管理器使通用对象被呈现为公共的绘制面。 显示混合器和表面/属性管理器管理通用对象共享的一组通用属性，并管理通用对象之间的附件。 第一个对象库在显示混合器中调用create-object函数来创建一个或多个第一个通用对象。 第一个对象库生成第一个通用对象的显示数据，显示混合器协调显示第一个通用对象的显示数据。