公开(公告)号：US20200294969A1

公开(公告)日：2020-09-17

申请号：US16355623

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Anh Phan ,  Caleb Shuan Chia Barrett ,  Jay Prakash Gupta ,  Nishant Gupta ,  Kaiwen Hsu ,  Byungki Jung ,  Srinivasa Aravind Killampalli ,  Justin Gary Railsback ,  Supanee Sukrittanon ,  Prashant Wadhwa

IPC: H01L25/065 ,  H01L27/085 ,  H01L29/78 ,  H01L21/84 ,  H01L27/06

Abstract: Disclosed herein are stacked transistors with dielectric between source/drain materials of different strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between source/drain materials of adjacent strata, and the dielectric material is conformal on underlying source/drain material.

公开(公告)号：US20200273962A1

公开(公告)日：2020-08-27

申请号：US16649933

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Prashant Majhi ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L27/22 ,  H01L27/24 ,  H01L29/49

Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

公开(公告)号：US20200266218A1

公开(公告)日：2020-08-20

申请号：US16279693

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/84

Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

公开(公告)号：US20200258881A1

公开(公告)日：2020-08-13

申请号：US16649712

申请日：2018-01-18

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/861 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66

Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

公开(公告)号：US10734511B2

公开(公告)日：2020-08-04

申请号：US16077742

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Rafael Rios

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L29/739 ,  H01L29/08

Abstract: An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.

公开(公告)号：US20200168703A1

公开(公告)日：2020-05-28

申请号：US15780619

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Seung Hoon Sung ,  Jack T. Kavalieros ,  Sanaz K. Gardner

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/201 ,  H01L29/08 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00

Abstract: Nanowire transistors including embedded dielectric spacers to separate a gate electrode from source and drain regions of the transistor. Embedded spacers are disposed within interior sidewalls of a passage through which the gate electrode wraps around a semiconductor filament. The presence of these embedded spacers may dramatically reduce fringe capacitance, particularly as the number of wires/ribbons/filaments in the transistor increases and the number of interior gate electrode passages increases. In some advantageous embodiments, embedded dielectric spacers are fabricated by encapsulating external surfaces prior to those surfaces becoming embedded within the transistor.

公开(公告)号：US10651313B2

公开(公告)日：2020-05-12

申请号：US16325423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Matthew V. Metz ,  Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Sean T. Ma

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/24

Abstract: An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.

公开(公告)号：US20200098753A1

公开(公告)日：2020-03-26

申请号：US16141000

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/267 ,  H01L29/10 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US20200020805A1

公开(公告)日：2020-01-16

申请号：US16490502

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: Disclosed are systems, methods, and apparatus directed to the fabrication of vertical field effect transistors (VFETs) and VFETs with self-aligned wordlines. In one embodiment, the source and/or drain of the VFETs can include n-doped silicon. In one embodiment, the VFETs can include a channel that can be made of intrinsic silicon. In one embodiment, the source, drain, and/or channel can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD), and the like. In one embodiment, an STI process can be used to fabricate one or more recesses, which can reach the drains of the VFETs. In one embodiment, the systems, methods, and apparatus can permit the self-alignment of one or more wordlines of the VFETs with the one or more fins, and/or gate metals and gate materials of the VFETs.

公开(公告)号：US10483353B2

公开(公告)日：2019-11-19

申请号：US15778863

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/092 ,  H01L29/786

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).