公开(公告)号：US10713750B2

公开(公告)日：2020-07-14

申请号：US15477018

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06T1/60 ,  G06F12/127 ,  G06F12/0815 ,  G06F12/123

Abstract: An apparatus to facilitate cache replacement is disclosed. The apparatus includes a cache memory and cache replacement logic to manage data in the cache memory. The cache replacement logic includes tracking logic to track addresses accessed at the cache memory and replacement control logic to monitor the tracking logic and apply a replacement policy based on information received from the tracking logic.

公开(公告)号：US20200218330A1

公开(公告)日：2020-07-09

申请号：US16819385

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Joydeep Ray ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Kamal Sinha ,  James M. Holland ,  Pattabhiraman K. ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Carson Brownlee ,  Vivek Tiwari ,  Kai Xiao ,  Jefferson Amstutz ,  Deepak S. Vembar ,  Ankur N. Shah ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06F1/3218 ,  G06T1/20 ,  G06F1/3234 ,  G06F9/46

Abstract: An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed.

公开(公告)号：US10691617B2

公开(公告)日：2020-06-23

申请号：US16113174

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Prasoonkumar P. Surti ,  Balaji Vembu ,  Wenyin Fu ,  Bhushan M. Borole ,  Kamal Sinha

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0811 ,  G06F13/40 ,  G06T1/60 ,  G06F12/0897 ,  G06F12/084

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

公开(公告)号：US10691392B2

公开(公告)日：2020-06-23

申请号：US15488758

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Eric J. Asperheim ,  Subramaniam M. Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC: G06F3/01 ,  G06F3/14 ,  G09G5/391 ,  G06F3/0484 ,  G09G5/00

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US20200160564A1

公开(公告)日：2020-05-21

申请号：US16659907

申请日：2019-10-22

Applicant: Intel Corporation

Inventor： Altug Koker ,  Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T9/00 ,  G06T1/20

Abstract: A mechanism is described for facilitating fabric-based compression and/or decompression of data at computing devices. A method of embodiments, as described herein, includes compressing contents of a data stream traveling through an internal fabric between a source component and a destination component, wherein the contents are compressed on the internal fabric.

公开(公告)号：US20200111454A1

公开(公告)日：2020-04-09

申请号：US16599175

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan K. Bhiravabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G09G5/00 ,  G06F9/46 ,  G06F12/0875

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US10607392B2

公开(公告)日：2020-03-31

申请号：US16405353

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  David I. Standring ,  Shruti A. Sethi ,  Jeffrey S. Frizzell ,  Alan M. Curtis ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06T15/00 ,  G06F12/02 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/10 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0811

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.

公开(公告)号：US10591971B2

公开(公告)日：2020-03-17

申请号：US15477010

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Joydeep Ray ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Kamal Sinha ,  James M. Holland ,  Pattabhiraman K. ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Carson Brownlee ,  Vivek Tiwari ,  Kai Xiao ,  Jefferson Amstutz ,  Deepak S. Vembar ,  Ankur N. Shah ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06F1/32 ,  G06F1/3218 ,  G06T1/20 ,  G06F1/3234 ,  G06F9/46

Abstract: An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed.

公开(公告)号：US10573066B2

公开(公告)日：2020-02-25

申请号：US16215850

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US10565676B2

公开(公告)日：2020-02-18

申请号：US15488547

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.