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    Technologies for transparent function as a service arbitration for edge systems
    111.
    发明授权
    Technologies for transparent function as a service arbitration for edge systems 有权

    公开(公告)号：US10798157B2

    公开(公告)日：2020-10-06

    申请号：US16234734

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Ned Smith ,  Kshitij Doshi ,  Alexander Bachmutsky ,  Suraj Prabhakaran

    IPC: H04L29/08 ,  H04L12/24

    Abstract: Technologies for function as a service (FaaS) arbitration include an edge gateway, multiple endpoint devices, and multiple service providers. The edge gateway receives a registration request from a service provider that is indicative of an FaaS function identifier and a transform function. The edge gateway verifies an attestation received from the service provider and registers the service provider. The edge gateway receives a function execution request from an endpoint device that is indicative of the FaaS function identifier. The edge gateway selects the service provider based on the FaaS function identifier, programs an accelerator with the transform function, executes the transform function with the accelerator to transform the function execution request to a provider request, and submits the provider request to the service provider. The service provider may be selected based on an expected service level included in the function execution request. Other embodiments are described and claimed.

    Selective execution of cache line flush operations
    112.
    发明授权
    Selective execution of cache line flush operations 有权

    公开(公告)号：US10691594B2

    公开(公告)日：2020-06-23

    申请号：US16023717

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Vadim Sukhomlinov ,  Kshitij Doshi

    IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0891

    Abstract: The present disclosure is directed to systems and methods that include cache operation storage circuitry that selectively enables/disables the Cache Line Flush (CLFLUSH) operation. The cache operation storage circuitry may also selectively replace the CLFLUSH operation with one or more replacement operations that provide similar functionality but beneficially and advantageously prevent an attacker from placing processor cache circuitry in a known state during a timing-based, side channel attack such as Spectre or Meltdown. The cache operation storage circuitry includes model specific registers (MSRs) that contain information used to determine whether to enable/disable CLFLUSH functionality. The cache operation storage circuitry may include model specific registers (MSRs) that contain information used to select appropriate replacement operations such as Cache Line Demote (CLDEMOTE) and/or Cache Line Write Back (CLWB) to selectively replace CLFLUSH operations.

    Systems, methods and apparatus for fabric delta merge operations to enhance NVMeoF stream writes
    114.
    发明授权
    Systems, methods and apparatus for fabric delta merge operations to enhance NVMeoF stream writes 有权

    公开(公告)号：US10664396B2

    公开(公告)日：2020-05-26

    申请号：US15724311

    申请日：2017-10-04

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Kshitij Doshi ,  Sujoy Sen

    IPC: G06F12/0813 ,  G06F3/06 ,  G06F12/0868 ,  G06F9/50

    Abstract: A method and apparatus for performing a data transfer, which include a selection a data transfer operation mode, based on telemetry data, from a first operation mode where a first type of data is transferred from a memory of a computing system to one or more shared storage devices, and a second operation mode where a second type of data is transferred from the memory to the one or more shared storage devices, the first type of data being associated with a first range of address space of the one or more shared storage devices, the second type of data being associated with a second range of address space of the one or more shared storage devices different from the first range of address space. Furthermore, a data transfer from the memory to the one or more shared storage devices in the selected data transfer operation mode may be included.

    TECHNOLOGIES FOR ACCELERATED ORCHESTRATION AND ATTESTATION WITH EDGE DEVICE TRUST CHAINS
    115.
    发明申请
    TECHNOLOGIES FOR ACCELERATED ORCHESTRATION AND ATTESTATION WITH EDGE DEVICE TRUST CHAINS 审中-公开

    公开(公告)号：US20190230002A1

    公开(公告)日：2019-07-25

    申请号：US16368980

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Kapil Sood ,  Tarun Viswanathan ,  Kshitij Doshi ,  Timothy Verrall ,  Ned M. Smith ,  Manish Dave ,  Alex Vul

    IPC: H04L12/24 ,  H04L29/06

    Abstract: Technologies for accelerated orchestration and attestation include multiple edge devices. An edge appliance device performs an attestation process with each of its components to generate component certificates. The edge appliance device generates an appliance certificate that is indicative of the component certificates and a current utilization of the edge appliance device and provides the appliance certificate to a relying party. The relying party may be an edge orchestrator device. The edge orchestrator device receives a workload scheduling request with a service level agreement requirement. The edge orchestrator device verifies the appliance certificate and determines whether the service level agreement requirement is satisfied based on the appliance certificate. If satisfied, the workload is scheduled to the edge appliance device. Attestation and generation of the appliance certificate by the edge appliance device may be performed by an accelerator of the edge appliance device. Other embodiments are described and claimed.

    NON-VOLATILE MEMORY AWARE CACHING POLICIES
    118.
    发明申请
    NON-VOLATILE MEMORY AWARE CACHING POLICIES 有权

    公开(公告)号：US20190042416A1

    公开(公告)日：2019-02-07

    申请号：US16015880

    申请日：2018-06-22

    Applicant: Intel Corporation

    Inventor： Kshitij Doshi ,  Bhanu Shankar

    IPC: G06F12/0804

    Abstract: In embodiments, an apparatus may include a CC, and a LLC coupled to the CC, the CC to reserve a defined portion of the LLC where data objects whose home location is in a NVM are given placement priority. In embodiments, the apparatus may be further coupled to at least one lower level cache and a second LLC, wherein the CC may further identify modified data objects in the at least one lower level cache whose home location is in a second NVM, and in response to the identification, cause the modified data objects to be written from the lower level cache to the second LLC, the second LLC located in a same socket as the second NVM.

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